According to the characteristics of digital processing applications, loop buffering can be used to reduce the power consumption of instruction memories while fetching instructions.
但是，根据数字信号应用的特点，可以采用循环缓冲来减小指令存储器的功耗。
A buffering based cache-oblivious nest-loop parallel join algorithm is proposed.
提出了一种基于缓冲的高速缓存参数无关的嵌套循环并行连接算法。
A buffering based cache-oblivious nest-loop parallel join algorithm is proposed.
提出了一种基于缓冲的高速缓存参数无关的嵌套循环并行连接算法。
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