Logic simulation is a necessary step in design of ASIC.
逻辑模拟是ASIC设计中必不可少的一个环节。
Complex business logic simulation with runtime variable state machine.
包含运行时变量状态机的复杂业务逻辑模拟。
Fault simulation is reduced to logic simulation on the original circuit.
故障模拟被简化为在原始电路上的逻辑模拟。
With the rapid growth of complexity of VLSI, more and more logic simulation has adopted parallel discrete event simulation.
随着大规模集成电路的复杂性日益增加，逻辑模拟开始采用并行离散事件模拟技术。
Waveforms are used as a tool for describing circuits during logic simulation and accurate simulation is achieved by computing and checking waveforms.
在逻辑模拟中用波形作为电路状态的描述工具，通过对波形的计算和检查实现精确的模拟。
This method is based on multi-delay modeling, SPICE and logic simulation. It provides an effective tool to design and analysis asynchronous data-path.
这种方法在进行性能分析时基于多延迟模型、SPICE和逻辑仿真，可以作为异步数据通路设计和分析的一种有效工具。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
Difierent from event oriented logic simulation system widely being used, we present a new design method-wave form and some relative algorithms, which are thoroughly process-oriented.
异于目前广泛采用的面向事件的模拟系统，本文提出了基于面向过程的波形字逻辑模拟系统的结构、设计和实现方法，并给出了系统中使用的主要算法。
With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.
有了适当的工具支持，设计人员可以在高层的系统模型上进行执行或模拟，并调试，从而在早期确认并验证系统逻辑。
Using business item instances in a simulation can be useful, particularly if you want to test your logic, or run a simulation based on real data.
在模拟中使用业务项实例非常有用，特别是希望测试逻辑或者根据实际数据运行模拟时更是如此。
The computer simulation for the designed circuits by using SPICE program confirm that both circuits have correct logic functions, desired DC transfer characteristics and transient characteristics.
应用SPICE程序对设计电路的计算机模拟表明，两种电路均具有正确的逻辑功能、理想的DC转移特性和瞬态特性。
The locking logic for avoiding wrong operation in normal operation training is one of the difficulties in the development of the Substation's Simulation and Training System.
正常操作培训防误操作闭锁逻辑是仿真培训系统的开发中的一个难点。
Therefore, an improved logic implication algorithm has been proposed, which was inspired by the by the single pass deductive fault simulation algorithm.
因此，我们引进了一种新的寻找逻辑蕴涵的方法，该方法的灵感来自于单通道演绎故障的模拟算法。
Parallel discrete event simulation based on TW is an effect method to improve the speed of simulation, it's common implementation structure is distributed logic process structure.
基于时间偏差的并行离散事件模拟是提高模拟速度的有效手段，其通用系统实现结构是分布式逻辑进程模拟结构。
This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介绍了VHDL逻辑级模拟系统中模拟模块的设计和实现。
Separating solving logic from multibody dynamics model, the consistency of status of constraint and force element component was achieved in multibody dynamics system simulation.
这种解算模式，实现了多体动力学解算仿真中，模型与解算逻辑的分离，维护了系统仿真中构件、铰约束、力元等组件的状态一致性。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
The results of simulation prove that the improved algorithms are feasible for evolving the digital combinational logic circuits and improve the evolvable efficiency and convergence performance.
仿真实验结果证明了改进演化算法对于实现函数级数字组合逻辑电路的硬件演化是可行的，并且提高了演化算法的演化效率和收敛性能。
Configuration of component and simulation scheme in varies solving logic was optimized, and make it was made concurrent developing and simulation convenient based on component.
利于在不同的解算逻辑下组件和仿真方案的配置，方便了基于组件的协同开发与仿真。
Controller was designed in MATLAB fuzzy logic toolbox, and fuzzy controller and taxiing model were used in SIMULINK condition, and the whole simulation model was set up.
在MATLAB模糊逻辑工具箱中对控制器进行设计，并将模糊控制器与滑跑模型应用于SIMULINK仿真环境，建立整体仿真模型。
It is proved that this type of counter has correct logic function according to EDA simulation and experimental verification with FPGA and can be normally used in the design of digital system.
经eda软件模拟仿真和FPGA硬件验证，表明该计数器具有正确的逻辑功能，能够正常地应用于数字系统的设计。
According to the semi classical model, the transfer characteristics of CMOS type single electron digital logic cells were analyzed by the Monte Carlo simulation.
根据单电子系统半经典模型，采用蒙特卡罗法单电子模拟程序对电容耦合的类CMOS单电子逻辑单元在不同参数条件下的转移特性进行数值模拟。
The simulation result is that the Fuzzy forward neural networks which is trained by this algorithm have good non-logic generalization and feature extraction ability, as well as fast learning speed.
模拟结果表明利用该算法训练的模糊层次神经网络具有较好的非逻辑归纳能力和特征抽取能力，并且学习速度也大大加快。
The demand for actual equipments of the network simulation detection is reduced by simulating a single device into multiple virtual devices in logic.
通过将单台设备模拟为逻辑上的多台虚拟设备，减少了网络模拟测试对实际设备的需求量。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模拟结果表明所设计的触发器具有正确的逻辑功能，跟传统的时钟低摆幅双边沿触发器相比，降低近17%的功耗。
The paper designs and implements a simulation system of ACBAC to verify the validity of the logic model in the actual application.
本文实际设计并实现了ACBAC模拟系统，验证了上述逻辑模型在应用中的有效性。
The paper designs and implements a simulation system of ACBAC to verify the validity of the logic model in the actual application.
本文实际设计并实现了ACBAC模拟系统，验证了上述逻辑模型在应用中的有效性。
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