A real time optical logic processor is presented, that can perform binary logic operations in parallel. Experimental result is given of the system as a half adder.
本文提出了一种能实时完成二进制逻辑运算的光学并行处理系统，并给出了作为半加法器的实验结果。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
A logic element designed to act as either an adder or a subtracter in accordance with the control signal applied to it.
根据供给它的控制信号，或起加法器作用或起减法器作用的一种逻辑元件。
A computer is comprised of some logic parts which have serial logic functions, and the adder is one of the combine logic circuits.
电子计算机是由具有各种逻辑功能的逻辑部件组成的，加法器就属于其中的组合逻辑电路。
Finish the design of data path, including adder, shifter, ROM and the control logic of the rotation, and optimize these parts in terms of the requirement of Longtium C2 microprocessor.
完成超越函数实现的数据路径设计，主要包括加法器、移位器、常数rom和旋转控制逻辑，同时针对“龙腾”C2微处理器的性能要求对各个部件进行优化设计。
The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU), while the adder decides that of the ALU.
算术逻辑运算单元（ALU）决定着中央处理器（CPU）的性能，而加法器又决定着ALU的性能。
On the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement, through logic synthesis and layout.
首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。
In the ALU, we integrate the method of equinoctial node-group and conditional sum adder to design reconfigurable ALU, and join negative logic circuit design design principle into it.
在ALU设计中，将二分结组的思想和条件求和相结合设计了可重组的ALU，并加入负逻辑的数字电路设计思想。
In the modern computer, the adder being present in the arithmetic logic unit.
在现代的电脑中，加法器存在于算术逻辑单元之中。
A fast carry-skip adder is proposed based on variable-sized two-level block carry-lookahead logic.
提出了一种基于方块超前进位的快速进位跳跃加法器。
We gave logic device of the 8bit full-adder of flow work. Introduce apple of the flow work on PLD design.
用八位全加器的工作，说明了流水线技术在PLD设计中的应用。
The circuits such as ternary full-adder, etc. designed by using this theory can have simpler circuit structures and correct logic functions. It is confirmed that this theory is efficient in...
应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能，从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。
The circuits such as ternary full-adder, etc. designed by using this theory can have simpler circuit structures and correct logic functions. It is confirmed that this theory is efficient in...
应用该理论设计的三值全加器等电路具有简单的电路结构和正确的逻辑功能，从而证明了该理论在指导电流型CMOS电路在开关级逻辑设计中的有效性。
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