Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Through carefully analyze and optimize the structure of circuit, now the circuits have been designed, pre-layout simulation and portion of layout design have been completed.
对电路结构进行了仔细分析和优化设计，完成了电路设计和前仿真和部分版图设计。
In this paper, summary to the question that the layout design of the Storage Logistics System, we develop one simple, effective Simulation System with three-dimensional technology.
本课题针对仓储物流系统的规划设计所存在的问题，利用三维仿真技术，开发一种简单，有效的仓储物流仿真系统。
Firstly by introducing the layout engine, it makes the simulation of browser to display Web page and getting all kinds of visual features possible.
首先通过引入布局引擎，使得模拟浏览器显示并获得网页中各表格的视觉特征成为可能。
The researches in this thesis are facility layout, visualization and process simulation of manufacturing Cell according to the layout problem of manufacturing system.
本文针对制造系统布局问题研究了制造单元设备布局方法和布局方案的可视化及运行仿真技术。
In this paper, through numerical simulation, reasonable layout of ventilation outlet and optimal configuration are researched.
通过数值模拟，对机械排风口的合理布置位置和最佳配置方式进行了研究。
Run a defrag Simulation that lets you simulate a defrag in compressed time so you can see your drive layout before you actually defrag!
模拟运行碎片整理，让你在压缩的时间模拟碎片整理，以便可以看到你之前，你的驱动器布局实际上碎片整理！
After the runner layout and gate size were decided, it could adjust runner size iteratively based on the of flow simulation results.
利用流动模拟结果，在流道布置及浇口尺寸确定后对分流道尺寸进行优化。
System simulation is an efficient technology for system layout. It can offer real and reliable data for system layout through its special way. It can also shorten the period of system development.
系统仿真是一种有效的系统规划和设计技术，它以其独有的方法为系统的规划设计提供客观、可靠地定量数据，缩短系统建设周期。
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The paper has an emphatical discussion on the study and analysis of the circuit structure and layout structure of these two modules, and makes a lot of SPICE simulation and verification.
课题着重对这两个模块的电路结构以及版图结构进行了深入的研究和分析，并采用SPICE工具进行了模拟验证。
It can also offer a direct verification and evaluation of the layout design through the contrast between the simulation of the original layout scheme and the optimized one.
系统可以根据用户输入参数给出较优的设备布局方案，并可通过布局方案性能指标对比，对布局方案进行直观的验证和评价。
The paper describes a CAD tool, it can perform GaAs device simulation, device parameter abstraction, circuit simulation, layout edition and PG tape generation.
介绍了一套砷化镓专用电路CAD软件，它可完成砷化镓器件模拟、器件模型参数提取、电路模拟、版图编辑、PG带生成的全过程设计。
In this article, the modeling technology in environment simulation is introduced combined with making Olympic Games layout propaganda animation.
该文结合奥运规划宣传片的制作，介绍了环境模拟中涉及到的建模技术。
Calculation and simulation of a variety of melting furnace structure layout, and get the law of heat transfer and fluid flow processes of glass current.
计算和模拟了不同的窑池结构布置时，玻璃液的传热和流动方式过程。
Science visualizing is to display result on 3-d data field using visualizing technology. It consist of simulation of logic layout, the after-treat and alternation-treat of result.
科学可视化运用可视化技术在三维数据场上显示科学计算结果，包括逻辑布局的仿真模拟、计算结果数据的后处理和交互处理。
This paper design an audio processor through circuit designing, simulation, layout designing, chip testing. PMS1345 is an I2C bus controlled audio processing IC chip.
这次毕业设计从电路设计、性能仿真、版图设计、芯片整合测试这几个方面出发，设计出一款的音频处理芯片pms1345。
In this thesis, we illustratre the theory of the chip, system design, partition of the modules, simulation and realization of analog circuit and layout design.
本文对芯片工作原理、系统架构设计、模块划分、前端模拟电路实现、版图设计等进行了详细分析。
Design flow of analog circuit begins with drawing schematic and includes simulation, layout, DRC/LVS check, parasitic extraction and post-simulation.
在完成版图设计后，还进行了几何规则检查和版图与电路一致性的 检查。
Design flow of analog circuit begins with drawing schematic and includes simulation, layout, DRC/LVS check, parasitic extraction and post-simulation.
在完成版图设计后，还进行了几何规则检查和版图与电路一致性的 检查。
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