Two main aspects in VLSI testing, fault simulation and test generation, are researched in this dissertation.
本文对VLSI测试中的两个主要问题—故障模拟和测试产生进行了深入的分析和研究。
This paper describes state transition fault and collapsing of test generation basis of the character of fixed fault.
详细分析了固定故障所反映出的状态变换特征，提出状态变换故障模型以及相对应的测试生成压缩方法；
The result indicates that the technology manipulates easily and is effective, the fault coverage reaches 90%, it is a feasible test generation technology.
仿真结果表明，该方法操作简单、有效，故障覆盖率达到了90%，是一种很可行的存储器板测试生成方法。
The implementation of automatic test generation and fault diagnosis is also discussed.
还讨论了测试码自动生成和故障诊断的具体实现方法。
The test generation algorithm for non-robust path delay fault in combinational circuits is studied.
研究了组合电路中非鲁棒性路径时滞故障的测试生成算法。
Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm.
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。
This paper propose a functional fault for delay faults in combinational circuits and describe a functional test generation procedure based on this model.
提出一种用于测试组合电路中延迟故障的新功能故障模型，讨论该模型的功能测试生成。
This paper proposes a new algorithm for transient current test (IDDT) generation for delay fault.
这里提出了一种关于延时故障的测试产生算法。
Base on the existing synchronous sequential circuits fault simulator-HOPE, the test vector generation method of sequential circuits based on ant algorithm is systematically researched firstly.
本文在同步时序电路故障模拟器—HOPE的基础上，率先对基于蚂蚁算法的时序电路测试矢量生成方法作了系统的开拓性研究。
This paper studies the crosstalk fault and its methods of test pattern generation in high-speed interconnect circuits.
本论文针对高速互连电路串扰型故障及测试生成方法进行研究。
Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。
Based on the stuck-at fault analysis, state test generation for synchronous circuits is presented.
通过分析时序电路固定故障的状态变换，提出基于状态隐含变换的测试方法。
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