The refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
Thee refresh cycles are usually performed by a peripheral called a DRAM controller.
刷新周期一般由一个叫DRAM控制器的外设完成。
Then, when the external reset signal is disabled, a delayed reset signal DLYRST is generated and applied to the DRAM controller so that it is reset.
然后，当使外部复位信号无效时，生成一个延迟的复位信号并将其加到DRAM控制器以将其复位。
While the internal reset signal is being applied to the CPU, the rate of a refresh signal being generated by a DRAM controller for refreshing data in DRAM is increased.
在将内部复位信号加到CPU的同时，提高由DRAM控制器所生成的用于刷新DRAM中数据的刷新信号的速率。
It is mainly composed of DMA controller (82c37), interrupt controller (82c59), programmable interval timers (82c54), DRAM refresh control, wait state generator and system reset logic.
其内部主要由DMA控制器(82c37)、中断控制器(82c59)、可编程间隔计时器(82c54)，DRAM刷新控制器，等待状态产生器，系统重置电路组成。
The invention discloses a controller of a dynamic random-access memory (DRAM) and a user instruction treatment method.
本发明公开了一种动态随机访问存储器（DRAM）的控制器及用户指令处理方法。
The invention discloses a controller of a dynamic random-access memory (DRAM) and a user instruction treatment method.
本发明公开了一种动态随机访问存储器（DRAM）的控制器及用户指令处理方法。
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