The implementation carries out the standard-cell design of RS decoder, improves the velocity of decoding efficiently and simplifies the hard - ware design.
该方法实现译码器的标准单元化设计，并且有效提高译码的速度，简化硬件设计。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
At present, more and more communication system use LDPC code as the channel coding scheme, the architecture in this paper will give a reference to design and implementation of other LDPC decoder.
目前越来越多的通信系统采用LDPC码作为纠错码，这种硬件结构对其它系统的LDPC译码器设计及实现有一定的借鉴意义。
Because the decoding complexity of H. 264 is very high, software implementation can't decode in real time. The decoder must be implemented in hardware.
由于H . 264的解码复杂度很高，软件实现难以满足实时性的要求，所以需要采用硬件解码。
An implementation method and the implementation result of HDTV video decoder bit stream distribution circuit are given out in this paper based on the HDTV video stream construction.
文中在介绍高清晰度电视视频码流结构的基础上，提出了高清晰度电视视频解码器中码流分配电路的实现方法，并给出了实现结果。
Chapter 3 presents the design and implementation of memory management of RTOS for the HDTV integrated source decoder chip.
第三章具体描述应用于HD TV信源解码芯片的实时操作系统存储管理策略的设计及实现。
This paper introduces a method of hardware implementation in channel decoding, giving an emphasis on the decoding of punctured code and synchronization module following Viterbi decoder.
文中提出了信道译码硬件实现的一种方案，解决了其中删节码的解码和Viterbi译码后同步等难题。
The paper items from a project on developing communication devices. The implementation of CRC-RS decoder in the project asks for an adoption of RS and extended shortened CRC codes.
本论文内容来源于某通信设备研制项目，该项目中的“CRC-RS译码器的设计”要求采用RS和扩展缩短CRC码来实现。
Receiver general by the receiving circuit, amplifier, demodulator circuits, instruction decoder circuit, drive circuit and the implementation of the circuit composed of several parts.
接收器一般由接收电路、放大电路、解调电路、指令译码电路、驱动电路和执行电路几部分组成。
Encoding instruction decoder for decoding command signals, and finally by the drive circuit to drive the implementation of circuit operation to achieve a variety of commands.
指令译码器将编码指令信号进行译码，最后由驱动电路来驱动执行电路实现各种指令的操作。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
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