CPU的缓存机制。
It's unfortunate, but keeping the CPUs busy makes up for the problem of a CPU cache being cold for a migrated task.
不幸的是，保持CPU繁忙会出现CPU缓存对于迁移过来的任务为冷的情况。
In a computer with the contrasting von Neumann architecture (and no CPU cache), the CPU can be either reading an instruction or reading/writing data fROM/to the memory.
在基于冯诺依曼架构的计算机中（没有CPU缓存），CPU或者从存储器中读取指令或数据，或者在存储器中写入数据。
If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
When a thread is running on a CPU and gets interrupted, it usually gets placed back on the same CPU because the processor's cache might still have lines belonging to the thread.
当某个线程在一个CPU上运行并发生了中断，通常会将它放回到相同的CPU上运行，因为这个处理器的缓存中仍然保存了属于该线程的相关信息。
For example, suppose a task executed on CPU-1, and its data was in that processor's cache.
例如，假设一个任务正在CPU - 1上执行，其数据在这个处理器的缓存中。
This increases the latency of the task's memory access until its data is in the cache of the new CPU.
这就增加了任务的内存访问延迟，这些时间用来将其数据移入新cpu的内存中。
Reusing static content from the cache greatly improves client performance, reducing both bandwidth consumed and server CPU cycles.
重用缓存中的静态内容大大改善了客户端性能，减少了带宽消耗和服务器CPU周期。
CPU has been designed to maximize overall system performance and has significantly improved cache performance over previous-generation devices.
CPU的设计最大限度地优化整个系统的性能，并显著提高缓存性超过了前一代产品。
For example, if the environment does not have a lot of CPU power and the nature of the end user requests are most likely different each time, using the Query Plan Cache would not make sense.
例如，如果环境没有大量cpu功率，且终端用户请求的性质每一次可能不同，使用QueryPlanCache就没有意义。
In addition, cache using double dual ports RAM is used to save process time and other resource of CPU, we use LPC2106 cored by ARM as CPU.
另外还采用了两块双口ram缓存结构，节省了CPU处理时间与其他资源，CPU采用基于ARM内核的LPC 2106。
In a computer using the Harvard architecture, the CPU can both read an instruction and perform a data memory access at the same time, even without a cache.
在使用哈佛架构的计算机中，即使没有缓存，CPU也可以在读取指令的同时进行数据访问。
CACHE is not legal tender in most countries, but a type of memory that your CPU (central processing unit) first looks for.
缓存并非在多数国家的法定货币，一种记忆，但你的CPU(中央处理器)第一面貌。
This text analysis the structure and work elements of cache memory, the procession of cache memory, and the expect to the performance of CPU.
本文分析了高速缓存的结构和工作原理，阐述了高速缓存的工作过程以及对处理器性能的影响。
The next time the CPU reads the same address, the data is transferred from the cache memory instead of from main memory.
当CPU下次读取相同地址时，数据将从高度缓存中而不是主存储器中传出。
Fermi has a lot of cache and supports instructions that use to be common only for CPU and many people believe that this is a hybrid between a graphics card and a CPU.
费米有大量的缓存，并支持使用说明只有CPU和许多人的共同认为，这是一个图形卡和一个CPU的混合体。
As a result, the CPU instead shifts the old contents of the cache.
结果，CPU将缓存区的旧数据进行移位操作。
Without getting too technical, the new A-series APUs are made using a 32nm manufacturing process and each processor core on the "CPU side" of the APU has 1mb of its own Level 2 cache.
没有得到太多的技术，新的A系列的APU使用32纳米的制造工艺和每个处理器核心上的“CPU侧”的APU拥有自己的二级缓存1MB。
However you can raise the sample size to 10 at the cost of some additional CPU usage in order to closely approximate true LRU, and check if this makes a difference in your cache misses rate.
你可以提升样品大小配置到10，它将接近真正的LRU算法，并且有不同错过率，但是要消耗更多的CPU。
When the CPU reads data from main memory, a copy of this data is stored in the cache memory.
当CPU从主内存中读取数据时，一份数据拷贝将被存储在高速缓存中。
CPU problems can often be fixed by disabling the CPU internal cache in the BIOS.
CPU的问题往往可以通过禁用固定cpu的内部高速缓存在BIOS中。
CPU problems can often be fixed by disabling the CPU internal cache in the BIOS.
CPU的问题往往可以通过禁用固定cpu的内部高速缓存在BIOS中。
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