Finally, start MyObservable's clock to see output like that in Listing 6.
最后，启动myobservable时钟，查看如清单6所示的输出。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
If a mark is to be transmitted, the output goes high after the rising edge of the clock.
如果一个标志是要传输时，输出变为高电平后，在时钟的上升沿。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
Based on the system clock and trigger input signals, using FPGA to generate trigger output signals in given working modes.
通过FPGA实现在一定系统时钟和触发信号作用下各种工作模式的触发信号的产生。
The design of CPLD has adopted the output clock of image sensor to write SDRAM.
CPLD电路设计采用图像传感器的输出时钟触发sdram写过程。
The flip-flops are attached to each other in a way so that the output of one acts as the clock for the next, and so on.
触发器以这样的方式相互联接，使一个触发器的输出成为下一个的时钟，依此类推。
The resulting timing error is output to a write clock compensator.
将所得定时误差输出到写时钟补偿器。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The LED driver includes a clock supply to periodically output a modulation period.
此LED驱动器包括可周期性地输出调变周期的时脉源。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
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