提出同步时序设计的“心跳法则”，总结了以软描硬的调试理论。
The heart rule of synchronization timing design was proposed. The debugging theory of software for hardware was summarized.
针对某航空相机的设计要求，提出了一种可行的多模式驱动时序设计方法。
Put forward an available method aimed at the requirements of aerial camera with multi-mode.
在软件设计中，主要完成了FPGA的驱动时序设计和ARM的主控程序设计。
In software designing, the main driver to complete the FPGA design and ARM timing master programming.
针对某高帧频CCD可见光相机的设计要求，提出一种可行的驱动时序设计方法。
Put forward an available method aimed at the requirements of CCD visible light camera with high frame rate.
数据的跨时钟域传输对于长期仅接触同步时序设计的设计者而言是一个巨大的挑战。
It is a great challenge to a designer who is only familiar with the single clock-domain design.
自启动预载接口芯片以控制为主，时钟关系复杂。时序设计是整个设计的重点和难点。
Interface and download chip is control-oriented and has complex clock relationships, therefore timing design is the key and difficult point.
对于系统中复杂且高速的逻辑控制及时序设计及其实现的阐述是论文的另一重要部分。
Also, this paper details the complex and high-speed logic control and timing schedule design.
利用FPGA完成复杂且高速的逻辑控制及时序设计，将采集的图像根据视频信号原理进行裁剪并存储在SRAM中。
FPGA is used to achieve the complex and high-speed logic control and the design of time sequence, with grabbed digital video signal cut and stored in SRAM, under the principles of the video signal.
时序图是在模型开发过程中从设计到分析阶段最重要的部分。
Sequence diagrams are a mainstay in the overall process of moving your model driven development process from design to analysis.
当然，度量意指测试，且这些指标应该在测试中根据试验测定，因为时序随设计的不同而有所不同。
Of course, measuring implies testing, and these metrics should be measured experimentally in testing, as the timings vary from design to design.
在异步时序电路设计中，它将时钟方程和状态方程的求解归在统一的符号卡诺图上进行。
In design of pulsed asynchronous sequential circuits, it will solve for equations of clock and equations of state, on a symbolic Karnaugh map.
该方法摒弃了传统的基于流程图的设计思路，将软件的时序与逻辑分离，模块性好，结构清晰，软件的开发、维护方便。
Compared to conventional software design based on flow chart, the protection software is developed based on relay function module, which leads to the separation of time sequence and logic.
文章对数字集成电路设计中的时序分析作了一个概要的介绍。
The timing analysis in the design of digital integrated circuits is described.
本文提出一种异步时序电路设计的符号卡诺图的新方法。
This paper presents a new method of asynchronous design is illustrated by the symbolic Karnaugh map.
本文系统地分析了按常规设计步骤得到的111系列检测器的时序。
In this paper the 111 train detector derived by common design method has been analyzed systematically.
本文主要论述了CMOS图像传感器时序控制电路的系统设计和实现方法。
The system design and implementation methods of timing control circuit for a new CMOS image sensor are proposed.
本文提出异步时序电路的设计方法。
A method of designing asynchronous sequential circuits is presented.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Sequential logic synthesis is an important part of RTL synthesis system design.
这些方法对于正确使用触发器和设计时序逻辑电路有重要应用参考价值。
The methods have useful reference value to using correctly flip-flops and designing sequential logic circuits.
在时序逻辑设计中，较好地解决了数据的存储、读取和点像元数据连续监测。
Data storage, reading and continuous monitoring of point pixels have been well solved in design of time sequence logic.
选择部分典型工程进行造价分析，提出内河航运工程在建设时序上及工程设计中值得考虑的问题。
Based on the cost analysis of typical projects, this paper puts forward matters of attention concerning construction sequence and engineering design of inland navigation projects.
本论文主要论述了CMOS图像传感器时序控制电路的系统设计和实现方法。
The system design and implementation methods of timing control circuit for anew CMOS image sensor are proposed in the paper.
研究并设计了符合PCI规范V2.2的接口芯片，着重阐述了它的功能特点、时序特征及其大致设计流程。
In this paper, an ASIC based on PCI Local Bus SpecificationV2.2 is designed, and its function, timing characteristic and design flow are also presented.
设计人员通常在时序分析上花大量的时间和精力，因为一个微小的时序问题能导致整个设计的逻辑功能的错误。
Designers have to spend most of time and energy on timing analysis, because a slight mismatch would lead whole failure of entire logic function.
本文提出了逻辑法设计时序控制电路的改进方法。
An improvement of logic design approach for time-sequence control circuit is presented.
针对阀控模块中，MCU初始化或意外复位是管脚状态不确定导致可能的灾难性事故给出上电时序化设计。
Aiming at the possible fatal accident caused by uncertain IO states when valve control MCU is initializing or accidentally resetting, the method of power up timing design is presented.
对城区雨水利用分区、规划设计指引、建设时序等方面提出规划设想，给出相关政策建议。
Planning ideas for rainwater utilization district zoning, a design guide, and the time sequence for construction are provided, and policy Suggestions are made.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
介绍了用EPROM进行时序电路设计的原理、方法和应用实例。
The article gives the principle, method and applied example of the EPROM used as sequential circuit design.
介绍了用EPROM进行时序电路设计的原理、方法和应用实例。
The article gives the principle, method and applied example of the EPROM used as sequential circuit design.
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