PPE用载入和存储指令访问主存储器(有效地址空间)，可以在主存储器与内容可以缓存的私有寄存器文件之间移动数据。
The PPE accesses main storage (the effective-address space) with load and store instructions that move data between main storage and a private register file, the contents of which may be cached.
一个存储器地址是由输出到适宜的总线上的二进制数据所组成。这个总线我们称为地址总线。
A memory address consists of binary data being output on an appropriate bus which we call the address bus.
在一些系统中，指令存储器比数据存储器更大，所以指令地址的宽度要高达数据地址。
In some systems, there is much more instruction memory than data memory so instruction addresses are wider than data addresses.
端口0也是复低位地址和在利用外部程序和数据存储器的数据总线。
Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory.
对微控制器而言，PDIUSBD12看起来就像一个带8位数据总线和一个地址位（占用两个位置）的存储器件。
To a micro-controller, the PDIUSBD12 appears as a memory device 8-bit data bus and 1 address bit (occupying 2 locations).
数据采集系统触发电路、随机采样短时间产生电路、存储器地址计数器电路等相关控制电路的设计、仿真和调试；
The circuits revelent to data acquisition system such as trigger circuit, the circuit of short time generator in random sampling etc, are designed, simulated and adjusted.
静态存储器的存取速度由地址输入到数据输出的关键路径决定。
The access rate of the memory is determined by crucial path which is between data input and data output.
采用了两种存储器对数据分类记录，对数据记录内容和芯片存储地址空间进行了合理分配。
It use two types of memory to record the data so the design distribute the storage address space and choose the recording content.
当CPU下次读取相同地址时，数据将从高度缓存中而不是主存储器中传出。
The next time the CPU reads the same address, the data is transferred from the cache memory instead of from main memory.
当CPU下次读取相同地址时，数据将从高度缓存中而不是主存储器中传出。
The next time the CPU reads the same address, the data is transferred from the cache memory instead of from main memory.
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