The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。
The difference clock delay match technology adjusts the two channel AD analog clock phase and implements the two way AD uniformly-space sampling.
差分时钟延迟匹配技术通过对两路AD的采样时钟进行相位调整，实现了两路AD的等间隔采样。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
To test for this scenario, rig up an external phase-locked dual-clock source with a knob that intentionally adjusts the phase relationship of the two clocks.
为了测试这个，做一个外部相位锁定的双时钟源，带有两个时钟有意调节相位关系的节点。
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