The invention relates to the test field of integrated circuits and discloses a low power consumption test pattern generator of an integrated circuit and a test method thereof.
本发明涉及集成电路测试领域，公开了一种集成电路的低功耗测试图形生成器及其测试方法。
A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode.
耦合到单个存储器的模式发生器操纵在并行测试方式过程中使用的并行测试矢量和在扫描测试方式过程中使用的并行和扫描测试矢量。
A pattern generator coupled to the single memory manipulates the parallel test vectors used during the parallel test mode and the parallel and scan test vectors used during the scan test mode.
耦合到单个存储器的模式发生器操纵在并行测试方式过程中使用的并行测试矢量和在扫描测试方式过程中使用的并行和扫描测试矢量。
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