The expression is validated in Synopsys device simulation tools MEDICI.
表达式用MEDICI器件模拟软件进行了验证。
The circuit functions are verified with altera FPGA chips and the results of the verification and its ASIC synthesis with Synopsys DC are given.
同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据。
The circuit functions are verified with altera FPGA chips and the results of the verification and its ASIC synthesis with Synopsys DC are given.
同时还给出了采用现场可编程门阵列(FPGA)芯片对设计电路进行功能验证的结果和ASIC流片的基本数据。
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