A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
Since this decoder has high error-correcting speed and regular structure, it may apply to data transmission and storage to decrease error rate.
由于该译码器有较高的纠错速率和规则的设计结构，使它可以方便地用于数据传输和存储过程中进行差错控制。
The encoder and decoder is optimized for high-speed modern communications technology, particularly in the higher hardware resources environment.
该编码器和译码器适合用于高速率的现代通信技术，特别是硬件资源较丰富的环境。
The encoder and decoder have such advantages as small size, good performance and high speed.
该编译码器具有体积小、性能稳定、工作速度高等优点。
The encoder and decoder have such advantages as small size, good performance and high speed.
该编译码器具有体积小、性能稳定、工作速度高等优点。
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