In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.
论文中设计了一种高密度的译码器电路架构，同时针对阵列提出了解决读取和编程时存在的阵列横向导通电流问题。
In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.
论文中设计了一种高密度的译码器电路架构，同时针对阵列提出了解决读取和编程时存在的阵列横向导通电流问题。
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