The lower value of CPI means one instruction takes less time to execute. The cycles can be broken down into several parts in terms of how much time is spent in different pipeline stage.
CPI值低就意味着指令花费的执行时间少。
Branch mis-prediction (Processor guesses the wrong branch, so it has to flush the pipeline and load instruction from proper branch again), or.
分支预测错误(处理器猜错了分支，所以它不得不更新流水线并从正确的分支装载指令)。
Setting up instructions so that they take full advantage of a processor's pipeline is called instruction scheduling.
对指令进行设置使它们可以充分利用处理器流水线的技术称为指令调度。
Again, taking POWER5 as an example, the time an instruction stays in the pipeline can be divided into three parts.
同样以POWER 5为例，指令在流水线中停留的时间可以划分为三个部分。
This allows more latency hiding and less instruction pipeline stalls, and the code runs faster as a result.
这将允许更多的延迟隐藏和更少的指令管道摊位，和代码运行更快。
For architecture level ones, this paper introduces three kinds of optimization methods, which called operation optimization, instruction optimization and pipeline optimization.
在平台级优化方面，给出了操作优化、指令优化以及流水线优化等三种优化方法。
In the instruction execution pipeline stage, scalable pipeline technology was adopted to realize the video processing instruction.
为有效实现扩展指令，处理器执行级采用了可扩展流水级技术。
Combining with features of ASIP architecture, study on application specific low power optimization technology focusing on instruction set (program code), pipeline and storage.
结合ASIP体系结构特征，以应用特征为指导，针对指令集(程序代码)、流水线和存储部件进行了低功耗优化研究。
Data hazard rise when an instruction depends on the results of aprevious instruction in a way that is exposed by the overlapping of instructions in the pipeline.
数据风险上升 ，当一个指令的结果依赖于前一个指令的方式公开的重叠在管道的指令。
The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline.
该检验指令会对于每个线程单独地向下传输到各个流水线中，直到它到达每个流水线末端的缓冲器。
Brief instruction is given to principle of pipeline automatic welding in all positions, types and character of welding torch swing methods.
并简要介绍了管道全位置自动焊原理、焊枪摆动方式和特点。
A system performance model of high performance microprocessor is implemented, which is based on superscalar pipeline technology with the instruction set of i960KA.
本文讨论了系统性能模型在体系结构设计中的作用，研究了高性能微处理器的性能仿真模型设计技术。
A system performance model of high performance microprocessor is implemented, which is based on superscalar pipeline technology with the instruction set of i960KA.
本文讨论了系统性能模型在体系结构设计中的作用，研究了高性能微处理器的性能仿真模型设计技术。
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