A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
Upon the low power design consideration, a hybrid active-passive loop filter is employed and the signal summing block is removed by using discrete-time differentiation technique.
基于低功耗设计考虑，调制器采用有源-无源混合型环路滤波器，并通过离散时间微分技术移除信号求和模块。
The paper analyzes the design method of passive loop filter thoroughly, and presents a effective design method. The method has obvious advantage comparing to the design method in existence.
对锁相环的环路滤波器的设计方法进行了深入研究，给出了一种环路滤波器设计方法，该设计方法与现有设计方法相比具有较明显的优点。
This paper gives the design and experimental results of low noise NPLL frequency synthesizer and concludes that the passive loop filter is more suitable for low noise design than active loop filter.
介绍低相噪NPLL频率综合器的设计及实验结果。提出用无源环路滤波器比用有源环路滤波器更好，可获得低相噪设计。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
Noise which comes from both active and passive circuit element in loop filter will deteriorate phase noise of output signal.
环路滤波器中的有源和无源器件均有噪声产生，此类噪声会叠加在输出信号上，从而恶化输出信号的相位噪声。
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