Based on the full use of parallel architecture, an efficient solution for VLSI implementation is described.
在采用并行结构的基础上，给出了一种高效的VLSI实现方案。
According to the research on the existing VLSI architecture of the bit-plane coding, a new VLSI architecture is proposed in which stripe-column and coding are both implemented in parallel.
研究了现有的位平面编码VLSI结构，设计了一种条带列与编码通道全并行的VLSI结构，解决了内部存储资源占用率高的问题。
In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.
提出了比特平面并行处理的零树编码结构。
In this paper, we present a bit plane-parallel architecture for zero tree coding which is suitable for VLSI implementation.
提出了比特平面并行处理的零树编码结构。
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