A memory controller on the chip.
芯片上集成内存控制器。
On-chip L3 directory and memory controller.
芯片上L 3目录和内存控制器。
A memory controller is designed to stabilize the given system.
设计了一个“有记忆型”控制器。
The memory controller is coupled with a dynamic random access memory.
所述存储器控制器耦接一动态随机存取存储器。
In addition, the integrated memory controller will support only two channel DDR-3 instead of three.
此外，整合的内存控制器将支持只有两个频道解甲还乡- 3而不是三天。
The integrated memory controller is a trump of K8 architecture, and it shows its best in this test.
集成内存控制器的K8是杀手的建筑，它表明了最好的考验。
An embodiment of the invention discloses a method, memory controller and memory system for accessing PCIE RAM.
本发明实施例公开了一种访问PCIE RAM的方法、存储控制器和存储系统。
Parameter table module is the SDRAM memory controller interface for reading parameter information when image processing.
参数表模块主要实现SDRAM存储器的控制器接口，用于图像处理时读取参数信息。
The processors 5, 10 May each include a local memory controller hub (MCH) 15, 20 to allow communication with memories 15, 20.
处理器5和10可各自包括允许与存储器15和20通信的存储器控制器集线器(MCH) 15和20。
The image sensor has an integrated memory controller for controlling transfers of data between the sensor and the memory array.
所述图像传感器具有用于控制所述传感器与存储器阵列之间的数据转移的集成式存储器控制器。
A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed.
本发明揭示用于在总线业务减少的情况下执行存储器块初始化及复制功能的存储器控制器及方法。
The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value.
所述存储器控制器可通过接收存储器的开始地址、所述存储器的结束地址及填充值来执行所述存储器初始化。
Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a Shared interface.
本发明的实施例提供了一种用于通过共用接口访问非易失性存储器控制器和易失性存储器的方法和设备。
The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the Shared control signals.
该方法还包括通过共用控制信号发出指令到选定的非易失性存储器控制器和易失性存储器中的一个。
In this embodiment, system memory controller 402 is integrated on the central processor 400 to provide access to system memory 404 through interconnect 406.
在这个实施例中，系统存储控制器402集成到中央处理器400上，以便提供通过互连406对系统存储器404的访问。
In one embodiment, graphics local memory controller is also integrated on chipset 408 to provide access to graphics local memory 416 through interconnect 418.
在一个实施例中，图形本地存储控制器也集成到芯片组408上，以便提供通过互连418对图形本地存储器416的访问。
In another embodiment, the graphics processor and graphics local memory controller are both located on the same integrated chip as the central processor (not shown).
在另一个实施例中，图形处理器和图形本地存储控制器均与中央处理器设置在相同的集成芯片上(未示出)。
System memory controller 106, integrated on chipset 102 in one embodiment, provides central processor 100 access to the system memory subsystem 108 through interconnect 110.
在一个实施例中，集成到芯片组102上的系统存储控制器106对中央处理器100提供通过互连110对系统存储器子系统108的访问。
By putting this information on the FSB, the request agent lets other processors know how this transaction affects their caches, and how the memory controller (northbridge) should behave.
将这些信息放在前端总线中看，请求代理人让其他的处理器知道这种执行是如何影响缓存以及存储控制器(北桥)是如何运转的。
According to the practical application of target software in order to control the content of the user procedures memory controller, the controller and connecting the accused convenient target.
根据实际应用对象，将控制内容编成软件写入控制器的用户程序存储器内，使控制器和被控对象连接方便。
The SPE cannot read main memory directly, but instead must import and export data between the local store and main memory using DMA commands to a unit called the memory flow controller, or MFC.
SPE不能直接读取主存，相反地必须通过对内存流控制器(或mfc)的单元使用dma命令来在本地存储和主存之间导入和导出数据。
They are used for issuing DMA commands to the memory flow controller, handling SPE events, and reading and writing messages to and from the PPE.
它们可用来向内存流控制器发出dma命令、处理SPE事件、向PPE和从PPE读写消息。
The API for interacting with the memory flow controller (MFC) is provided by the MFC headers.
与内存流控制器(MFC)进行交互的API是由mfs头文件提供的。
The triple-channel controller will appear on both desktop and server/workstation offerings, and it will support three memory modules per channel.
三通道控制器将会出现在桌面/服务器处理器上，每个通道支持3个记忆模块。
Late last month, Samsung provided 1.2-V 2-Gbyte DDR4 unbuffered dual in-line memory modules (UDIMM) to a controller maker for testing.
上个月月底，三星曾将一款1.2V 2GB容量的DDR4unbuffered双列直插内存条样品送给了某家内存控制器厂商进行样品测试。
Source adapter controller - the source adapter controller has an in-memory "mailbox" that it monitors to pick up events and passes them to the corresponding collaboration.
源适配器控制器——源适配器控制器在内存中具有一个“邮箱”，它对此邮箱进行监视，以拾取事件，并将其传递到相应的协作中。
The essential hardwares of computer contain CPU, memory, interrupt controller, DMA controller, etc.
计算机硬件的核心器件有CPU、内存、中断控制器、DMA控制器，等等。
Controller 218 typically contains buffer memory for the user data being written to, or read from, the memory array.
控制器218通常含有缓冲存储器以用于将用户数据写入到存储器阵列或从存储器阵列读取用户数据。
Command data for controlling the flash memory device is input to the controller 218.
用于控制快闪存储器装置的命令数据输入到控制器218。
Command data for controlling the flash memory device is input to the controller 218.
用于控制快闪存储器装置的命令数据输入到控制器218。
应用推荐