Hungry Bunny is an arcade game, which requires skills, timing and logic.
饥饿的兔子是一个街机游戏，这需要一定的技巧，时序和逻辑。
Designers have to spend most of time and energy on timing analysis, because a slight mismatch would lead whole failure of entire logic function.
设计人员通常在时序分析上花大量的时间和精力，因为一个微小的时序问题能导致整个设计的逻辑功能的错误。
State- machine is used to implement the timing logic in CPLD, and the main codes written by VHDL language are given.
CPLD的接口时序逻辑控制功能采用状态机工作方式实现，并给出了用VHDL编写的主要源代码。
The HL-2A control system consists of timing system, PLC logic control system and feedback control system.
HL 2A控制系统由时序控制系统，逻辑控制系统和反馈控制系统三个部分组成。
Logic analyzer: 16 fast deep memory digital channels allow you to see key numerical and timing relationships.
逻辑分析仪：16个快速的深存储器数字通道让您看到关键的数值和定时关系。
We have optimized the hardware logic according to the timing requirement on datasheet, and solved the timing incompatibility between the dual-core processor TMS320VC5471 and the USB chip PDIUSBD12.
对照数据手册的时序要求优化硬件逻辑设计，解决了双核嵌入式处理器TMS320 VC 5471和USB芯片PDIUSBD12时序不兼容的问题。
The shortcoming of the article is the lack of the detailed study and design of other modules such as the register module and bit timing logic modules. Further work needs to be done later.
本文的不足之处是没有对其他模块如寄存器模块和位时序逻辑模块等进行详细的研究和设计，以后还需要做进一步的工作。
Alternating-direct-alternating circuit is adopted and CPLD is used as logic control device of power IGBT in main circuit of variance-frequency timing system.
变频调速系统主电路采用交-直-交形式，以可编程逻辑器件(CPLD)作为调速系统逆变电路功率开关器件IGBT的逻辑控制器件。
Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis.
使用时钟作为资料在定时关闭已经创造各式各样的问题，特别在逻辑和物理综合。
Specify digital circuit timing: setup and hold times and logic propagation delays.
指定数字电路时间∶安装和占用时间和逻辑传播延迟。
Within the logic level the characteristics of a system are described by logical links and their timing properties.
在逻辑门级，系统的特性使用逻辑链路和它们的时间属性。
Also, this paper details the complex and high-speed logic control and timing schedule design.
对于系统中复杂且高速的逻辑控制及时序设计及其实现的阐述是论文的另一重要部分。
Also, this paper details the complex and high-speed logic control and timing schedule design.
对于系统中复杂且高速的逻辑控制及时序设计及其实现的阐述是论文的另一重要部分。
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