The last part is Ethernet and JTAG circuit units.
其三是以太网数据交换电路与JTAG接口电路。
A general purpose JTAG Boundary-Scan Clock Cell is designed in this paper.
本文设计了一种通用的边界扫描时钟单元。
The paper introduces a simple but effective way to design a JTAG controller.
介绍了一种简单有效的JTAG控制器设计方法。
By the way, the average user won't JTAG his phone anyway so there's really no use.
顺便说下，一般的用户都不会JTAG他的手机，所以这方法没实际意义。
Embedded system based on ARM is composed of MCU, memory, JTAG circuit and power supply.
基于ARM的嵌入式系统的核心部分包括处理器、存储器、JTAG电路和电源部分。
The easy JTAG is introduced to control Test Access port (TAP) by computer parallel port.
采用简易JTAG接口，通过计算机并口控制测试访问端口。
For development purposes, you can load the FPGA directly from a host PC over a JTAG interface.
就开发目的而言，可通过JTAG接口直接从主机PC加载FPGA。
At the same time, also welcomed the ARM JTAG debug friends interested in the exchange of learning.
同时也欢迎对ARMJTAG调试感兴趣的朋友们一起交流学习。
As an IEEE test standard, JTAG is accepted and used by many IC design companies and manufacturers.
JTAG作为测试标准已为芯片设计与制造厂商接受和应用。
Finally, we also design the human-computer interaction circuit, serial interface circuit and JTAG circuit.
最后设计了人机交互电路、串行接口电路和JTAG电路。
This demodulation system also has serial port, parallel port, JTAG port, and can display signal wave in LCD.
本解调系统还拥有串口、并口等通信接口以及JTAG调试接口。自带lcd，可以动态显示解调后的信号波形。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
The paper proposes a JTAG customizing approach to managing all the DFT logic, for flexibility and less DFT overhead.
本文通过定制JTAG逻辑，以求用最少的开销，最简单灵活的方式来管理各种DFT逻辑。
Fault injection emulation platform based on Joint Test Action Group (JTAG) boundary scan and dynamic partial reconfiguration is proposed.
提出基于JTAG边界扫描技术和动态局部重配置的错误注入模拟平台。
In this paper, the principle of data collection, the basic function and implementation of asic and the technology of JTAG BST are presented.
介绍了数据采集的原理和ASIC的基本功能、实现以及JTAG的边界扫描测试技术。
Such chips can not interoperate with the JTAG or SGPIO protocols, or any other protocol that requires messages that are not multiples of 8 bits.
这种芯片没法和JTAG、SGPIO协议或者其它需要支持非8比特的整数倍的消息的协议进行交互。
This article gives a brief introduction to JTAG boundary scan basic protocol and describes in detail the structure, theory and algorithm of the system .
该文简述了边界扫描基本协议，详细介绍了本系统的结构和工作原理及其算法。
JTAG Boundary Scan is a new technique for connection test. With the help of JTAG, we can find out all connection faults of a complicated board or system.
JTAG边界扫描机制是用于在线导通测试的新技术，利用JTAG可以在数分钟内查出复杂插件和系统的全部导通故障。
This design will implement the communication through USB or serial interface, including serial download based on STK500 agreement and JTAG ICE simulation.
本设计能够使用USB接口或者串口两种接口进行通信，包括STK500协议的串口下载与JTAGICE仿真。
With Godson-1 processor as the research prototype, a verification method of processors on-chip-debugging function based on JTAG is presented in this paper.
以龙芯1号处理器为研究对象，探讨了基于JTAG的处理器在片调试功能的验证方法。
A discussion about two JTAG interfaces convenient to debug, extended Ethernet interface and the design of A/D interface converted from serial IIS by CPLD is carried out.
本文重点讨论了方便调试的两种JT AG接口、扩展的以太网接口和利用CPLD将串行I IS转换成并行总线的A/D接口的设计。
Joint test Action Group designed a common chip boundary-scan structure and test access port criterion which is called JTAG standard to support testing on-board chip or logic.
为支持板上芯片或逻辑的测试，联合测试行动小组专门设计和定义了一种通用的芯片边界扫描结构及其测试访问端口规范，称为JTAG标准。
The JTAG device Viewer interrogates and displays the state of the pins in any JTAG compliant device in your design in real time, helping you to analyze and debug your design.
JTAG器件视图可实时查询和显示设计中任意jtag器件管脚的状态，帮助用户分析和调试设计。
On the basis of research on the bound ary-scan architecture and TAP controller, the paper implements a design for a t ap interface based on JTAG specification in a test system.
该文在研究边界扫描体系结构和TAP接口控制器的基础上，在一个测试系统中，实现了基于JTAG规范的主ta P接口设计。
To enhance the stability of the system, design a lot of decoupling and bypass capacitors in hardware circuit. And the JTAG debug interface is designed for convenient debugging.
在硬件电路设计中，大量采用了性能较好的去耦和旁路电容来加强系统的稳定性，并为了调试方便设计了JTAG接口。
So the design of boundary scan is essential in the design of chips. IEEE instituted a standard for it, and the standard is IEEE1149.1 (that can be called as JTAG standard also).
边界扫描设计已逐渐成为芯片设计中不可或缺的部分，IEEE为其制定了相关标准，即ieee1149.1标准(也称为JTAG标准)。
The JTAG port and the RS232 serial port are designed to program in-situ. In teams of them, it is easily to adjust the circuit's working parameters or to update the control program.
整个系统可通过JTAG口和RS232串行通讯口进行现场编程烧录，能方便地调整电路的工作状态或实现硬件控制程序的升级、更新。
The JTAG port and the RS232 serial port are designed to program in-situ. In teams of them, it is easily to adjust the circuit's working parameters or to update the control program.
整个系统可通过JTAG口和RS232串行通讯口进行现场编程烧录，能方便地调整电路的工作状态或实现硬件控制程序的升级、更新。
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