Gate polysilicon is deposited over the gate oxide.
以及沉积于所述栅极氧化物之上的栅极多晶硅。
A transistor with a thin gate oxide being driven by too high of a voltage.
一个用薄栅氧化层电晶体被太多的驱动电压高。
The smaller feature size means thinner gate oxide, smaller voltage that gate oxide can endure.
因为特征尺寸的缩小意味着栅氧层的变薄，更小的电压就能够击穿器件的栅氧层；
TDDB(time-dependent dielectric breakdown)is a key method to value the quality of thin gate oxide.
经时绝缘击穿（TDDB）是评价薄栅氧化层质量的重要方法。
For gate oxide breakdown OTP memory, we present a viable NOR array structure and current sense amplifiers.
针对栅氧化层击穿otp存储单元提出了可行的阵列结构和电流敏感放大器。
A control gate having a thin gate oxide film is formed over a center channel portion of the channel region.
在沟道区的中央沟道部分上形成具有薄的栅氧化物膜的控制栅。
The surfaces of poly-Si thin film and gate oxide of thin film transistors were passivated using N2O/NH3 plasma.
采用N2O和NH3等离子钝化技术对多晶硅薄膜表面和栅氧表面进行了钝化处理。
Hot-carrier enhanced TDDB effect of ultra-thin gate oxide is investigated by using substrate hot-carrier injection technique.
本文通过衬底热载流子注入技术，研究了热载流子增强的超薄栅氧化层TDDB效应。
Also, High electric field annealing of stressed PMOSFET and detrapping of trapped electrons on the gate oxide are studied deeply.
重点研究了退化PMOS器件的高场退火效应和氧化层陷阱电子的退陷阱机制。
The simulated results indicate that thinner and longer channel can reduce short channel effects, while thicker gate oxide will lead to higher subthreshold slopes.
模拟结果显示：越细长的沟道，器件的短沟效应越弱，器件的亚阈值斜率随栅氧化层增厚而加大。
The first important thin film from the thermal oxide group is the gate oxide layer under which a conducting channel can be formed between the source and the drain.
第一个重要的来自热氧化组薄膜是栅氧化层，在它之下，源和漏之间就能形成导电通道。
The decrease of the gate oxide, the differences of field oxides processing and the selection of the substrate materials will all affect the total dose radiation effects of MOS devices.
器件栅氧厚度的减小、场氧工艺的改变以及衬底材料的不同等都将导致MOS器件的总剂量辐射效应发生改变。
Secondly, the transient characteristics of FN tunneling and hot hole (HH) stress induced leakage current (SILC) in ultra-thin gate oxide are investigated respectively in this dissertation.
其次，本文分别研究了FN隧穿应力和热空穴（HH）应力导致的超薄栅氧化层漏电流瞬态特性。
With taking advantage of the model of two-stage H+ process of interface trap formation and the role that F play in radiation hardness in gate-oxide . the above-mentioned result is deeply analyzed.
借助界面态建立的H~+两步模型和F在栅氧化层中对抗辐照加固所起的作用对上述结果进行了深入的分析。
At the corner of the gate polysilicon (14.3) and the polysilicon tiles (14.1 and 14.2) are oxide spacers (60.1-60.6).
栅极多晶硅（14.3）和所述多晶硅瓦 片（14.1和14.2）的角落处是氧化物间隔物（60.1-60.6）。
However, when oxide thickness increased to a fixed value at a specific oxide field, the increase in gate leakage current caused by a single oxygen vacancy could be neglected.
但当厚度在特定值及特定电场下时，单个氧空位引起的栅漏电流增加可以忽略。
A gate structure of the metal oxide semiconductor is etched (510).
将金属氧化物半导体的栅极构造蚀刻(510)。
A gate structure of the metal oxide semiconductor is etched (510).
将金属氧化物半导体的栅极构造蚀刻(510)。
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