If an equivalence check fails, the checker generates an input sequence of vectors that, when simulated, demonstrates the differences between the two circuits.
如果等价性检查失败，检查器会生成一个输入向量序列，它可以在仿真中使用以便演示两个电路之间的差异。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中，从而提高算术电路的验证能力。
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