A yield driven clock skew scheduling algorithm is proposed in presence of process variations.

针对工艺参数变化的情况，提出一种成品率驱动的时钟偏差安排算法。

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This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.

本文提出了一种有效的方法时钟歪斜调度中心可以减少误差平方和增量分配的休闲裤。

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A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.

提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。

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Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.

实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。

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Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.

实验结果表明：按权重分配裕量的方法相对于平均分配裕量，能够在不降低电路性能的情况下，更加有效地降低逻辑综合结果的面积。

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