An important problem in multi-clock domain design is how to avoid metastability.
多时钟域设计的一个难题是如何避免亚稳态的产生。
Whenever this happens, there is a possibility of meta-stability in the receiving clock domain.
这样，就在接收端所在的时钟域中造成了亚稳态。
Designers traditionally think of SRAM in its most basic form, a single-ported, single-clock domain device.
设计人员总把SRAM作为其最基本的形式，即单端口、单时钟域器件。
A grain is connected to one or more clock domains and attached to at least one power domain, and includes defined signals and conditions for power control.
一粒被连接到一个或多个时钟域并连接到至少一个电源域，并且包括定义的信号和用于功率控制的情况。
It is a great challenge to a designer who is only familiar with the single clock-domain design.
数据的跨时钟域传输对于长期仅接触同步时序设计的设计者而言是一个巨大的挑战。
The real time clock module provides is divided into an analog and a digital domain.
实时时钟模块提供的是分为模拟和数字域名。
An administrator is configuring the clock tolerance for the Single Sign-On token configuration policy and wants to define the time skew tolerance between a client and the domain controller clock.
管理员正在配置sso令牌配置策略的时钟容差，想要定义客户端和域控时钟之间的时间斜公差。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
Based on Gaussian random process model and continuous-time system in time domain, this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
该文从时域连续信号角度出发，按照高斯随机过程模型，分析了时钟抖动对基带和中频线性调频信号信噪比的影响并给出了近似公式。
应用推荐