该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
本文采用逻辑电路实现了基于采样数据的EPLL数字锁相环算法，并在FPGA电路中实现和实验验证该设计。
Through the adoption of the logic circuits, this article will successfully actualize the EPLL, which is based on the sample data, and validate this project in FPGA.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
实验结果表明，与传统的锁相环控制器及查询表式模糊控制器相比，采用调整因子式模糊逻辑控制器具有捕获速度快、鲁棒性强、启动成功率和稳定性高的特点。
The experimental results show that the fuzzy control system based on regulating factor has the most robust and fast control and the highest reliability compared with the others.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。
Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
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