所用的电路为蔡氏电路和锁相环电路。
锁相环电路，相移方法，及集成电路芯片。
Phase-locking loop circuit, phase shifting method, and IC chip.
本文研究了电荷泵锁相环电路的模型和电路设计。
This dissertation presents a study on modeling and circuit design of Charge Pump Phase-Locked Loops.
为满足高速和精确的采样，论文在控制器硬件中设计了锁相环电路。
The PLL circuit has been designed in the controller to meet the requirement of high-speed and accurate sampling.
本机工作在UHF频率，采用PLL锁相环电路，预设256个可选择使用频率。
This system works on UHF frequency brand, use PLL circuit. There are 256 frequencies for your option.
设计具体的锁相环电路，并建立利用锁相环技术检测荧光寿命的荧光温度传感器系统。
The fluorescence thermometry system in which the fluorescence lifetime is detected by phase-locked loop is established, and the specific phase-locked loop circuit is designed.
随后，本文详细讨论了并网过程中的软件锁相环技术，对锁相环电路的组成、工作原理进行了研究。
Subsequently, the detailed discussion of the software phase-locked loop technology and network process, the composition of the phase-locked loop circuit, the working principle of the study.
由于锁相环电路具有的窄带、跟踪、滤波等优点，因此在现有的雷达系统中，普遍采用由锁相环构成的频率综合器。
Frequency synthesizer composed of PLL is widely used in radar system because of PLL specialties such as narrow band, signal tracking and filter.
对于其中的单稳态电路的数字化和数字锁相环提取位同步信号也进行了详细的设计说明。
The digital realization of monostable circuit and extraction of bit-synchronous signal with digital phase lock loop are also introduced in detail.
分析了锁相环的基本原理和实现，并对射频电路设计理论和阻抗匹配问题进行了探究。
Analyzing the basic theory and development of PLL, and studying the design theory and impedance match problem of experimental circuit board.
本文详细分析了QF1052B型标准信号发生器锁相环部分的基本组成及其工作原理，并提出了对此部分电路的检测方法。
This paper gives a detailed analysis of the principle of the phase lock circuit, one of the most important parts of the QF1052B Standard Signal Generator and provides some methods of checking it.
本文采用逻辑电路实现了基于采样数据的EPLL数字锁相环算法，并在FPGA电路中实现和实验验证该设计。
Through the adoption of the logic circuits, this article will successfully actualize the EPLL, which is based on the sample data, and validate this project in FPGA.
介绍了锁相环的基本原理和锁相环ne564的电路结构和性能，及其用ne564构成的锁相解调电路和锁相倍频电路。
Introduces the basic principle of phase-locked loop and NE564 PLL circuit structure and properties, and the use of phase-locked NE564 demodulating circuit and phase-locked frequency circuit.
本文提出一种简单的跟踪滤波器电路，该电路可用于多普勒雷达，主要由开关式带通滤波器和锁相环组成。
This paper presents a simple tracking filter circuit, which is applicable to Doppler radar sets and consists mainly of a switched bandpass filter and a phase-locked loop.
本文设计的控制器以TMS320F2812DSP芯片为核心，加上检测电路（包括采样电路、调理电路、锁相环等）和其它外围控制和驱动电路构成。
The controller make up of TMS320F2812 DSP chip, detecting circuits include sampling circuit, modulate circuit and phase locked loop and other periphery control and drive circuit.
介绍一种高精度数学晶闸管触发器，它基于锁相环同步，适用于双反星形整流电路，并已成功地应用于晶闸管弧焊电流微机控制系统。
Digital thyristor Trigger of High Accuracy is introduced, which is based on phase locked loop synchronization and suitable for dual antistar rectification circuit.
由准同步视频检波的特点及其存在的问题引出锁相环（ PLL）完全同步视频检波电路。
The PLL full synchronization video detector circuit is educed by feature and troubles of quasi-synchronization video detector.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
应用锁相环集成电路ne567对音频信号的鉴相原理实现对控制信号的译码输出，控制井下仪器马达工作。
The latch phase circle circuit NE567 functions as phase demodulation of audio frequency signals for realizing decoding output of the control signals to control the downhole motor operations.
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
本文提出了一种无需整周期采样、无需锁相环和复杂电路硬件的相位检测算法。
A novel phase detection algorithm that does not need complete period sampling, phase-locked loops or complex electrocircuit hardware was presented in this paper.
本文给出了一种采用自偏置技术的低抖动延迟锁相环，可应用于高频时钟产生电路。
In this paper, a low-jitter process-independent DLL(delay locked loop) based on self-biased techniques is presented.
介绍了锁相环的基本原理，分析了锁相环各部分电路相位噪声的传递函数。
The basic principle of phase locked loop (PLL) has been introduced, and the transmission function of the phase noises of every part of PLL has been analyzed.
在数字延迟锁相环设计中，先整体讲述电路的整体构架的设计，然后详细阐述了基本模块的实现方法与原理。
During the design of delay - locked loop, the frame of the whole circuit is introduced and then the principles and implementation of the basic modules are presented.
并利用锁相环设计了同步信号发生器电路，解决了系统同步问题；
The problem of synchronization of the whole system is solved through sync signal generator circuit applying phased-locked frequency multiplier;
本文叙述了用CD 4046锁相环实现频率自动跟踪的电路结构和工作原理。
This paper describes the electronic structure of which automatic frequency-tracking has been implemented with help of IC model CD4046 and its operating principle.
结合锁相环的特性，设计一种电容式微机械陀螺双环路自激驱动电路。
Considering the characteristics of PLL, the dual self-excited driving circuits for capacitance micro-machined gyroscope are designed.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
本文的目的是研究目前应用最广的电荷泵锁相环的噪声特性以寻找减小环路噪声的电路架构。
The objective of the thesis is to explore the noise sources in PLL and find the proper circuit structures to reduce the noise effects.
应用推荐