阈值电压的逻辑电平降解能力的检查。
Voltage threshold capability checks for logic level degradation.
输出逻辑电平改变状态时的输入电压。
The input voltage at which the output logic level changes state.
绝对参量公约中最常见的例外就是温度和逻辑电平。
The most common exceptions to the use of the absolute magnitude convention are temperature and LOGIC levels.
着重阐述逻辑电平转换、控制逻辑的结构设计及其工作方式。
The structural design of logic level shift and control logic circuits are dealt with in particular.
在一个数据锁存如果LE是低，时钟是在高或低的逻辑电平举行。
The a data is latched if le is low and clock is held at a high or low logic level.
如果你选择DOUT(数字)，单选按钮高低似乎改变其逻辑电平。
If you chose DOUT (digital out), radio buttons LOW and HIGH appear to change its logic level.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
连接逻辑电路时，必须小心翼翼，以保证他们的逻辑电平和电流额定值是兼容的。
Care must be taken when connecting logic circuits to ensure that their logic levels and current ratings are compatible.
电路的电源电压为3 ~18V，适用于各种类型的数字逻辑电路的逻辑电平判断。
The circuit supply voltage is 3 ~ 18 v, suitable in logic level of kinds of digital logical circuits.
给出了调节设定逻辑电平阈值的计算公式和部分电路参数，使逻辑电平界限清楚，判断确切。
It supplies the account formulas and partial circuits parameters of the threshold value for adjusting and setting-up logic level. It makes logical level boundary clear and well-judged.
通过这种表示方式，我们已经明显考虑这样的事实：在通常的运算中，输出的逻辑电平是互补的。
In this notation we have explicitly taken account of the fact that in normal operation, as we shall see, the logic levels at the output are complementary.
一种硬件调试工具，能捕获实时电信号的许多逻辑电平(0或1)，逻辑分析仪在调试硬件问题和复杂的处理外设交互时相当有用。
A hardware debugging tool that can be used to capture the logic levels (0 or 1) of dozens, or even hundreds, of electrical signals in real-time.
多功能芯片ADT14既是一种输出逻辑电平控制信号的多点温度监控器，又是一种输出模拟电压信号的温度传感器，可广泛应用于各种嵌入控制系统中。
The multi-functional chip ADT14 is a kind of multi-point temperature monitor of outputting logic level control signal, It is also a kind of temperature sensor of outputting simulated voltage signal .
通过设置A0和A1输入端适当的电平，用逻辑控制的方法来选择所需的输出波形。
The desired output waveform is selected under logic control by setting the appropriate code at the A0 and A1 inputs.
本发明提供了电源电平升高的可编程逻辑器件存储器单元。
Programmable logic device memory elements with elevated power supply levels are provided.
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
低速单元采用带有电平恢复的传输管逻辑实现，高速单元采用动态传输门逻辑实现。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
根据单元级联多电平变换器拓扑结构及其脉宽调制技术的特点，以数字信号处理器和复杂可编程逻辑器件为核心，设计了多电平变换器的控制器。
On the basis of topology of cascaded multilevel convertor and its PWM technique, designed the controller of multilevel convertor at the core of DSP and CPLD.
然而，依照本发明可替换实施例，在数字信号处于逻辑低电平状态时，脉冲也可指时间周期。
However, according to alternative embodiments of the present invention, a pulse can refer to a period of time when a digital signal is in a logic low state.
高电压电平漂移电路允许低压逻辑信号来驱动的IGBT在高达1200V一种操作高侧配置。
High voltage level-shift circuitry allows low voltage logic signals to drive IGBTs in a high side configuration operating up to 1200V.
当设置到高电平逻辑（电路）时，两个扩音器都无声，处于低耗能（闲置）状态；当…
When set to logic high, both amplifiers are muted and in low power (…
然后分别介绍控制电路和主电路设计原理与思路，重点论述了混合电平逻辑设计中的接口解决方案、A/D采样电路、SPI通讯接口电路及主电路的保护等；
The key points lies in interface resolve method in hybrid voltage-logic design, A/D sampling circuit, SPI communication port and the protect of the main circuit.
当选择信号为逻辑高电平（1）时，乘法器510传输反相器504的输出信号给发生器404的输出作为输出信号VOUT。
When the select signal is a logic high (1), multiplexer 510 transmits the output signal of inverter 504 to the output of generator 404 as output signal VOUT.
通常，在数字信号处于逻辑高电平状态时，脉冲指时间周期。
Typically, a pulse refers to a period of time when a digital signal is in a logic high state.
在给定的道路循环下，考虑电池充放电平衡和发动机燃油经济性，提出了一种模糊逻辑控制策略。
Considering the batteries charge-discharge balance and the engine fuel efficiency under the given driving cycle, it is presented the control strategy using fuzzy logic.
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。
The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.
接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。
The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.
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