漏源极电压（图28）在反射过程结束后并减小到100伏特时场效应晶体管导通。
The drain-source voltage (Fig. 28) starts oscillating at the end of the flyback phase and reaching the minimum of 100V when the MOSFET turns on.
该电路还包括第二分支电路，该第二分支电路使得耦合到该电路的输出(34)的第二晶体管(25)在下降跃迁期间导通并接着被断开。
The circuit also includes a second subcircuit that causes a second transistor (25) that is coupled to the circuit's output (34) to turn on during a falling transition and then turn off.
本发明涉及一种具导通孔的电子元件及薄膜晶体管元件的制造方法。
The invention relates to an electronic element with a through hole and a manufacturing method for a film transistor element.
该保护电路不会导通。因此这种利用晶体管延时的保护电路完全可以作为CMOS集成电路电源和地之间的ESD保护电路。
So the given ESD protection circuit using transistor delay can be well applied to VDD-to-VSS ESD protection in CMOS IC.
该线电压极性检测电路检测线电压的 极性且控制该驱动电路以导通或截止该栅控晶体管。
The line voltage polarity detection circuit detects the polarity of line voltage and controls the drive circuit to conduct or cut off the gate-controlled transistor.
为管理芯片产生复位输入，其输入必须接收低有效的地信号，需要晶体管q 1导通。
To create an reset input to the supervisory chip, its input must receive an active-low ground signal, requiring transistor Q1 to turn on.
第一开关电路耦 接至电平转换器，并在第三晶体管导通时，关闭第四晶体管。
The first switch circuit is coupled to the electrical level translator and turns off the fourth transistor when the third transistor is turned on.
而第二开关电路耦接至电平转换器，并在第一晶体管导通时，关闭第二晶体管。
While the second switch circuit is coupled to the electrical level translator and turns off the second transistor when the first transistor is turned on.
而第二开关电路耦接至电平转换器，并在第一晶体管导通时，关闭第二晶体管。
While the second switch circuit is coupled to the electrical level translator and turns off the second transistor when the first transistor is turned on.
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