然后交错每个连续四进位输出符号的位，从而产生具有全局且交错的连串长度约束的输出比特流。
The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints.
在高速度和很少的电脑使用下数据采集系统获得数据是为进位输出提供必要，或合理的数据处理或简化。
Many or the data acquisition systems acquire this data at very high speeds and very little computer time is left to carry out any necessary, or desirable, data manipulations or reduction.
使所述四进位输出符号的位反相将产生具有(G,i)约束的输出比特流，如在反向串连调制系统中所使用的PRML (G, i)码中那样。
Inverting the bits of the 4-ary output symbols produces an output bit-stream with (g, I) -constraints as in the PRML (g, I) codes used in reverse-concatenation modulation systems.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
Addend and BeiJiaShu as input, and the device for output with binary for half a gal device.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
Addend and the summand input, and digital and carry the output device is a half adder.
输出信号频率通常可按十进位数字选择，最高能达11位数字的极高分辨力。
Output signal frequency can usually choose to decimal Numbers, to a maximum of 11-digit high resolution.
输出信号频率通常可按十进位数字选择，最高能达11位数字的极高分辨力。
Output signal frequency can usually choose to decimal Numbers, to a maximum of 11-digit high resolution.
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