译码器测试系统的设计和译码器性能测试是本课题另外两个重要环节。
Other two important tasks of our research project include the design of the verification system and the performance test for the decoder.
说明：利用两个8线译码器做成的一个十六线译码器。
Using a sixteen line decoder and made two of 8 line decoder.
该译码器可兼容多种码长、多种码率的LDPC码，因此只需要设计一个译码器，就可以完成对具有相同列重的不同LDPC码的译码。
Moreover, this decoder is also compatible with various block-lengths and code-rates, so only one decoder is needed for different LDPC codes with the same column weight.
分析了HDB3译码器的原理，提出了一种基于FPGA技术的HDB3译码器的快速实现方法。
The principle of HDB3 decoder is analyzed. A quick way to implement HDB3 decoder based on FPGA is proposed.
在达到设计要求的基础上本文对RS译码器做了进一步的研究，利用一种新型的复用流水线结构实现了多路RS译码器，有效的减少了每路译码所占用的资源。
In more research, a new multiplex pipeline is presented and is used to design multi-channel RS decoder. The proposed scheme greatly reduce resources per channel.
硬件实现结果表明，该译码器的资源利用率远远超过了传统的单码率译码器。
Hardware implementation results show that the resource efficiency of the multi-rate decoder is much better than that of traditional single-rate decoders.
编码器由8线- 3线优先编码器作为实例代表，译码器则包含3线- 8线译码器和2线- 4线译码器两个实例模块组成。
Encoders from 8-3 priority encoder for example, and decoder includes 3-8 decoder and the 2-4 examples of the two decoder modules.
本译码器采用改进的最小和译码算法及符合CMMB标准要求的部分并行译码器结构。
The decoder employs the Normalized MSA algorithm, and Partially Parallel structure for LDPC code in CMMB standard.
编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。
Encoder and decoder is a basic computer circuit devices. This Curriculum design by EDA design encoder and decoder.
编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。
Encoder and decoder is a basic computer circuit devices. This Curriculum design by EDA design encoder and decoder.
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