计数器输出通常为低，只在各自解码时间内变高。
The counter's outputs are normally low and go high only at their respective decoded time slot.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
以及其中将从所述计数器输出的计数值被提取作为转换后的数字输出值。
A count value output from the counter is extracted as a converted digital output value.
日志记录功能可用于收集性能数据，指定用户要监视的计数器，并且把数据输出到文件中。
A logging function is available to collect performance data, allowing the user to specify the counters to be monitored and output the data to a file.
这个实用程序的'-c'标志接受明文并输出加密的计数器部分。
The '-c' flag of this utility accepts the plain text and outputs the encrypted counter part of it.
这两种情况下，只要页计数器的值在起始页和结束页之间这一条件保持为真，selpg就会输出文本(逐行或逐字)。
In either case, as long as the condition that the page counter value is between the start and end pages holds true, it outputs the text (by line or by char).
当那个条件为假(也就是说，页计数器的值小于起始页或大于结束页)时，则selpg不再写任何输出。
When that condition is false, that is, the page counter is either less than the start page or greater than the end page, it does not write any output.
可以用netstat- s寻找缓存区拥挤的迹象，这个命令输出网络计数器的列表。
You can look for signs of buffer congestion with netstat -s, which prints a list of network counters.
对于不报告计数器值的任何输出列(例如基于状态的输出)，包装器直接返回底层监控表函数产生的数据，不做修改。
Any output columns that do not report counter values (for example, state based output) are returned directly from the underlying monitoring table function with no modification by the wrapper.
由单片计算机控制的计数器自动产生通1秒停4秒的信号，使5路继电器输出带动电喇叭轮流通电。
By single chip computer control of counter automatically generate tong 1 second stop 4 seconds of signal, make no. 5 relay output drive electric horn turns electrify.
有手动复位和电气输出信号的脉冲计数器。
数据选择器则将两个计数器中处于保持状态的奇偶数据交替输出，实现双边沿触发加法计数器的功能。
Data selector alternately to realize the functions of double edge trigger addition counter output the odd and even data in two counters.
通过使用可编程控制器中的专用脉冲输出指令和高速计数器，实现了对辐照仪步进电机的精确控制。
The accuracy control of the motors in Gamma-ray irradiation of blood is realized by means of the inner pulse output code and the high-speed counter in PLC.
机器将能够饲料产品的产品包装线添加选项“集产品供给单元与输出传送带计数器”。
The machine will be able to feed the product to the product wrapping line with adding the option of "set number product feeding unit with counter" to output conveyor.
复用开关的一个简单例子就是将单台设备的输出连接到2台仪器，例如一台伏特表和一台频率计数器。
One example of a multiple closure would be to route a single device output to two instruments, such as a voltmeter and a frequency counter.
由于供电后每个CD4017计数器的输出Q0都工作，所以不能在没有增加硬件的情况下得到20输出。
You cannot get 20 outputs without adding more hardware because of the fact that, upon powering up, each CD4017 counter displays output Q0 as being on.
没有延时时间，每个计数器上电后，计数输出是随机的，这样若干LED也许是亮的。
Without the delay time, each counter powers up with a random output count such that several LEDs may be on.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
数控分频器设计：对于一个加法计数器，装载不同的计数初始值时，会有不同频率的溢出输出信号。
Nc divider design: an adder counter, loading the initial count value, have different frequency output signal of the overflow.
FPGA的输出是固定频率、计数器和数字比较器使占空比可变的典型波形(表1)。
The output of the FPGA is typically a waveform with a fixed-frequency, variable-duty cycle, which a counter and a digital comparator generate (Listing 1).
本文采用GE -I系列可编程控制器（PLC）的计数器来模拟鼓形控制器，由于用软件来实现，因此编程、修改灵活方便，而且总步数和输出点数可以满足所有场合的需要。
GE-I Series PLC is used to simulate drum controller in this paper. Because of implement with software, it is easy to modify program, and its total steps, output points can be used in all conditions.
一比较器，接收上述第一计数器及上述第二计数器的计数值，以产生一致能信号输出；
The third counter starts counting in the first clock frequency when receiving the enabling signal, and stops counting when the enabling signal stops.
一比较器，接收上述第一计数器及上述第二计数器的计数值，以产生一致能信号输出；
The third counter starts counting in the first clock frequency when receiving the enabling signal, and stops counting when the enabling signal stops.
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