此类计数器设计方便，电路简单，译码电路简单，并具有快速自启动特。
These counters have many advantages: easy to design, simple circuit, simple decode and self starting.
本文介绍了一种同步测周期计数器的设计，并基于该计数器设计了一个高精度的数字频率计。
The design of a counter measuring synchronous period is introduced in this paper. And based on it, a high precision digital cymometer is designed.
介绍了一种光学颗粒计数器设计技术的理论和方法，并研制了一套用于颗粒计数的实验装置。
The particle count technology based on light scattering at different collecting angles is introduced and device is constructed.
为了弥补机械式凸轮控制器存在的众多缺点，利用欧姆龙系列plc的高速计数器设计了可编程凸轮控制器。
A programmable CAM controller, which will not have the disadvantages of a mechanical CAM controller, was designed based on the high-speed counter of Omron PLC.
通过对计数器和钟控传输门绝热逻辑电路工作原理及结构的研究，提出一种带复位功能的低功耗十进制计数器设计方案。
Based on the working principle, counter structure and Clocked Transmission Gate Adiabatic Logic circuits, a design scheme of decimal counter with reset is proposed.
本文介绍一种按规则序列设计的移位型计数器。此类计数器设计方便，电路简单，译码电路简单，并具有快速自启动特性。
In this paper, it introduces one kind of shift counters designed with regular sequences. These counters have many advantages: easy to design, simple circuit, simple decode and self starting.
探讨利用中规模计数器芯片设计按非自然顺序循环的任意进制计数器方法，该方法在特殊循环计数器设计的应用中，有着广泛的应用。
The method of design of arbitrary cany counter of unnatural sequence circulation by use of medium - scale counter core is discussed. It finds wide application in the special circulation counter.
本文是关于采用三个TTLD触发器和六个译码器来组成扭形计数器的设计。
This paper is concerned with three TTL D flip-flops and six Decoders which are buith by Ring counter design.
因为移位计数器的设计可查已有的反馈函数表达式，所以十分容易。
The design for shift counters is quite easy, because of the obtained feedback functions may be consulted.
它可以彻底消除由噪声引起的寄生脉冲，现已成功地应用于通用计数器的设计中。
It can quit clearly the autoeciousness impulses brought by the noise and it has been used in the design of general counter.
介绍一种以大规模集成电路为核心组成的通用计数器的设计。
The design of an universal electronic counter which mainly consists of LSICis introduced.
该文从消除时钟信号冗余跳变而致的无效功耗的要求出发，提出了应用并行技术和流水线技术，实现基于RTL级的双边沿触发计数器的设计。
To erase the bootless power dissipation of the redundant leap of the clock, this paper proposes the RTL design of double edge triggered counter using parallelism and pipeline technique.
运用计数器记录时间和路程，并在LED数码管上实时显示电动车行驶时间和路程，使得本设计更趋智能化，人性化。
Using internal counter to record traveled time and distance, and on led monitor real-time demonstration causes this design to hasten the intellectualization and the human nature.
介绍以中规模集成计数器为核心，结合中规模集成组合逻辑器件及少量门电路进行时序逻辑电路设计的方法。
This paper introduces one way to design scheduling logic circuit with medium-scale integrated counter at the core and based on MSI.
提出用纯二值结构的三值T触发器和普通的二值触发器一起构造混值N进制计数器的设计方案。
This paper proposes the design method of a mixedvalued modulo-N synchronous counter by using both common binary flip-flops and ternary T flip-flops which has binary structure.
介绍用通用阵列逻辑器件GAL设计十进制可逆计数器的方法。
The method of design of ten's carry reversible counter by use of common array logic element GAL is introduced.
针对人们运动量的不定量性，提出了便携式活动计数器的设计方法。
In view of the case that peoples sporting quantity is not quantitative, this paper introduces the design way of the easily - carried activity counter.
在此基础上，进一步提出了借助于三值K图化简技术，设计具有自校正功能的三值扭环形计数器的方法。
The design method of ternary Johnson counter with automatic correction is presented by means of ternary K-map minimization.
至于预设计数器集合中未提供的计数器，则可以利用负载测试编辑器来新增。
Counters not provided in the default set of counter can be added by using the Load Test Editor.
然后提出了反馈式和邻控式混值计数器的设计。
The design methods of the feedback type and neighbour-controlling mixed-valued counters are proposed.
借由指定图形要显示的负载测试计数器，即可以设计自订图形。
You design a custom graph by specifying the load test counters that the graph will display.
为实现逻辑大小的最小化，本设计只使用两个从0到7的整数和带进位的计数器。
To minimize the logic size, this design USES only two integers ranging from 0 to 7 together with a carry for the counters.
本文介绍了数字电路系统的逻辑设计过程，并且着重阐明异步计数器和译码器的功能，数字钟是这方面应用的一个实例。
This paper introduces the process of logic design of digital circuits, and mainly explains the function of asynchronous counter and decoder. The digital clock is an example of this application.
本文提出了动态身份认证的概念，并在基于手机为载体的系统上用j2me及asp.net设计并实现了一个基于计数器同步的动态身份认证系统。
This paper introduces the principles of dynamic identity authentication and develops a counter synchronization authentication system using mobile as the carrier with J2ME and ASP. NET.
最重要的是侧面，法恩斯沃思设计3d打印的盖革计数器。
On the side of that, Farnsworth designs 3d printable Geiger counters.
通过一个例子，分析了加法计数器的设计方法。
The ways for designing addition counter are studied through an illustration.
在以CPU3为核心的数据采集模块系统中，设计了传感器信号发生、调理电路及由计数器组成的数据采集电路。
In the module system of data gathering taking CPU3 as the core, the article describes the circuit of signal-arising of sensors, signal-converting of sensors, and data gathering using counters.
本文介绍一种按规则序列设计的移位型计数器。
In this paper, it introduces one kind of shift counters designed with regular sequences.
数据采集系统触发电路、随机采样短时间产生电路、存储器地址计数器电路等相关控制电路的设计、仿真和调试；
The circuits revelent to data acquisition system such as trigger circuit, the circuit of short time generator in random sampling etc, are designed, simulated and adjusted.
数据采集系统触发电路、随机采样短时间产生电路、存储器地址计数器电路等相关控制电路的设计、仿真和调试；
The circuits revelent to data acquisition system such as trigger circuit, the circuit of short time generator in random sampling etc, are designed, simulated and adjusted.
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