也导出了两方法的耗尽层宽度公式。
耗尽层-晶圆片上的电场区域，此区域排除载流子。
Depletion Layer - a region on a wafer that contains an electrical field that sweeps out charge carriers.
界面电位降与测量电容、薄膜电容及耗尽层电容有关。
The voltage drop of interface is relevant to the measured capacitance, the film capacitance and the depletion capacitance.
当施加反向偏置电压时，形成的耗尽层厚度变大，从而使热载流子的产生减到最小。
When a backward biasing voltage is applied, the thickness of a depletion layer formed is made large, so that generation of hot carriers is minimized.
本文分析了三探针测试硅外延片中雪崩击穿时耗尽层宽度的面接触模型，理论和实验结果吻合。
In this paper, the area contact model of depletion layer width under avalanche breakdown in Si epitaxial wafer by a three-probe method is analysed. The theory accords with experimental results.
利用泊松方程（零偏压时耗尽层宽度作为边界条件）积分计算出其电场分布、电势分布等重要结特性。
Some important characteristics, such as build-in electric field distribution, build-in potential distribution were calculated by poisson′equation.
在部分耗尽型SOI结构中，SOI中顶层硅层的厚度为50-90nm，因此沟道下方的硅层中仅有部分被耗尽层占据，由此可导致电荷在耗尽层以下的电中性区域中累积，造成所谓的浮体效应。
In partially depleted SOI, the top layer is between 50- to 90-nm thick. Silicon under the channel is partially depleted of mobile charge.
在部分耗尽型SOI结构中，SOI中顶层硅层的厚度为50-90nm，因此沟道下方的硅层中仅有部分被耗尽层占据，由此可导致电荷在耗尽层以下的电中性区域中累积，造成所谓的浮体效应。
In partially depleted SOI, the top layer is between 50- to 90-nm thick. Silicon under the channel is partially depleted of mobile charge.
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