在数据存储器和内存结构之间，有许多虚拟或后台处理器忙于处理sql语句。
Between data storage and memory structure, there are number of virtual or background processors that are busy with processing SQL statements.
通过把该数据结构的两个元素分离到两条不同的高速缓存线路，一条高速缓存线路的修改就不会导致再次从存储器读入另外一条高速缓存线路。
By separating the two elements of the structure into two different cache lines, modification of one cache line does not cause another cache line to be read in again from the memory.
IDS的基本体系结构包括三个主要组件：数据存储器、内存结构和后台处理器或虚拟处理器。
Basic IDS architecture has three major components; data storage, memory structure and background or virtual processors.
传统上讲，工作站的吞吐量与其总线和存储器体系结构以及CPU的速度有关。
Traditionally, a workstation's throughput depends on its bus and memory architecture, as well as its CPU speed.
在硬件上介绍了RTL8019AS网卡芯片的硬件结构和内部存储器结构，以及其收发数据包的方法。
It also introduce the hardware structure, the memory structure and the method of receiving and delivering datum bundle of RTL8019AS chip.
为了在计算机的存储器中实现堆栈结构，习惯上保留一个足够大的连续的存储单元，以适应堆栈，因为它的生长和收缩。
To implement a stack structure in a computer's memory, it is customary to reserve a block of contiguous memory cells large enough to accommodate the stack as it grows and shrinks.
本文讲述了DSP的CPU结构、存储器构成、外设资源和指令寻址方式等。
The paper introduces the CPU structure, Memory composition, Peripheral resources and the addressing modes of DSP.
介绍了均光波导多层存储器的基本结构和原理。
The structure and principles of the uniform scattering waveguide multilayer memory are introduced.
介绍了数字射频存储器(DRFM)技术在雷达对抗中的应用，描述了DRFM的结构和工作原理。
This paper introduces the applications of digital RF memory (DRFM) technology to the radar countermeasures, describes the structure and operational principle of DRFM.
该文分析了目前常用的快闪存储器的结构和特性，在此基础上介绍了基于NAND闪存的数码相机系统。
This paper introduces the structure and attributes of flash memory. And the digital camera system based on NAND flash memory is then presented and described.
本文介绍了闪速存储器的结构特点和工艺技术，并与EPROM和EEP - ROM电路进行了比较。
This paper introduces the FLASH MEMORY circuits technique and structure characteristic, also compared the circuits with that of EPROM and EEPROM.
这里提出的结构解决了这个问题，它利用标准CMOS晶体管来实现非易失性存储器，这样就不需要额外的掩膜或工艺步骤。
The proposed structure circumvents this problem by creating non-volatile memory cells from standard CMOS transistors. Thus, no additional masking or processing steps are necessary.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
对于温度传感器存储器的结构和使用要求做了一个详细的说明。
The temperature sensor memory of the structure and the use of a request to do a detailed description.
该系统采用DSP与PC构成主从式并行结构，共享存储器实现双机高速数据通信。
In this system the master-slave parallel structure is composed by DSP and PC. The dual machine high speed communication is implemented by the Shared memory.
一种集成电路包含存储器单元结构，其包含第一单元以及第二单元。
The first cell includes a first storage structure and a first gate over a substrate.
本文介绍一个新的具有两种类型存储器的控制流并行计算机结构。
This paper presents a new control flow parallel computer architecture using two types of memory.
存储器是计算机系统的重要资源之一，任何程序、数据和各控制数据结构都必须占用一定的存储空间。
Computer memory is an important system resources, any procedures data and the control data structure must occupy some storage space.
接着对H . 264编码器进行了结构优化、算法优化、汇编优化、和存储器分配优化。
After that, this paper carries out structural optimization, algorithm optimization, compilation optimization and memory allocation optimization on the H. 264 encoder.
在计算机科学中，信息在计算机存储器中的组织方式被称为数据结构。
In computer science, the way information is organized in the memory of a computer is called a data structure.
在详细分析了SDRAM和DDR存储器结构的基础上，提出了MBM的设计思想，并给出了其实现方法和实际波形。
Based on the analysis of the SDRAM and DDR memory architecture, this paper presents the design principals of MBM and offers the implementation and the actual waveforms.
最后，对它的可靠性进行了分析，并给出在同样的冗余下，它与备份形式的存储器容错结构的可靠性比较结果。
Finally, the reliability has been analysed and the reliability comparison result with strand-by memory fault-tolerance structure in the same redundancy has b...
本发明提供一种规划一存储器的方法、装置、系统及信息结构。
The present invention provides a method for planning a memory, its device, system and information structure.
本发明提供的具有缓冲层结构的电阻转变型存储器制造工艺简单、制作成本低并且与传统CMOS工艺兼容。
The resistance transformation type memorizer with a buffer layer structure has simple manufacturing process and low manufacturing cost, and is compatible to the traditional CMOS process.
对系统的存储器结构、数据通信通道组成和系统总线结构进行了分析；讨论了算法划分、算法的多处理器映射及调度；
The memory structure, constitution of data communication channel and system bus are analyzed, and the algorithm allocating, algorithm mapping and scheduling on the multiprocessor are discussed.
最后，对它的可靠性进行了分析，并给出在同样的冗余下，它与备份形式的存储器容错结构的可靠性比较结果。
Finally, the reliability has been analysed and the reliability comparison result with strand-by memory fault-tolerance structure in the same redundancy has been given.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
提出一种适用于NOR结构快闪存储器应用的，具有大驱动能力、低功耗和高精度特性的电荷泵系统。
A novel positive charge pump for NOR flash memory with high driving capability, high precision and low power consumption, is proposed in this paper.
研究表明，单电子环形存储器单元电路利用量子点环状电路结构形式，由外接输入电压控制各岛上的电荷，能够得到存储器的“0”和“1”状态。
It is shown that the two states('0' and '1') of single-electron ring memory, which has a cyclic array of quantum dots, can be implemented by input voltage controlling the charges on the islands.
研究表明，单电子环形存储器单元电路利用量子点环状电路结构形式，由外接输入电压控制各岛上的电荷，能够得到存储器的“0”和“1”状态。
It is shown that the two states('0' and '1') of single-electron ring memory, which has a cyclic array of quantum dots, can be implemented by input voltage controlling the charges on the islands.
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