一级封装中最流行的互连技术仍为丝焊。
Wire bonding is still the most popular interconnect technology in the first-level packaging.
文章论述了超csptm圆片级封装技术工艺。
This paper discusses a true wafer level packaging (WLP) technology which is called Ultra CSPTM.
它们可以分为圆片级封装、芯片级封装、和封装面。
They can be classified into wafer level, chip level, and package level stacking.
建立了板级封装的三维有限元模型并进行模态分析。
The 3-d finite element model is built for the modal analysis of board-level package.
为板级封装动态响应分析和焊料微互连应力分析提供了基础。
The reliability of solder interconnections is dependable on the dynamic response of the board-level package.
设计并制作了一种基于LTCC技术的系统级封装多通道射频前端电路。
A system in package(SIP) RF front-end based on LTCC technology was designed, fabricated and tested.
帕洛马技术3500III执行全自动晶圆级封装和先进的微电子组装。
Palomar Technologies Model 3500-III performs fully automatic wafer scale packaging and advanced microelectronics assembly.
本文对圆片级封装的定义、演变、进展状况及支撑技术进行了介绍和分析评论。
The difination, evolution, status and supporting technologies of wafer-level packaging are introduced and reviewed in this paper.
随着微电子封装密度的提高，板级封装在跌落冲击载荷下的可靠性成为人们关注的焦点。
With increase in electronic package density, the reliability of a board-level package under drop impact load becomes a key issue.
我打赌它也从iPhone的销售中获得了版税—并且会一直这样，直到它的关键芯片级封装专利在2010年期满。
I'd bet it is reaping royalties from iPhone sales too — and will until its key chip scale packaging patent expires in 2010.
阐述了MEMS的主要封装工艺和技术，包括圆片级封装、单芯片封装、多芯片组件和3d堆叠式封装等。
Moreover, some major processes package of MEMS, including wafer-level packaging, single-chip packaging, multi-chip packaging and stacked 3d packaging, etc were discussed.
对刚性基板倒装式和晶圆再分布式两种结构的芯片级封装（CSP）进行了研究，描述了CSP的工艺流程；
Chip scale package (CSP) for flip-chip on hard substrates and wafer re-distribution is studied, and its process flow is described.
所述结构可具有较不复杂的聚焦、减小的串扰、较紧密的像素组装密度、提高的量子效率及晶 片级封装。
The structure may have less complex focusing, reduced crosstalk, tighter pixel packing density, increased quantum efficiency, and wafer-level packaging.
该器件提供两种封装：32引脚架构芯片级封装（LFCSP）和25引脚晶圆级芯片规模封装（WLCSP）。
The part is available in a 32-lead lead frame chip scale package (LFCSP), and a 25-ball wafer level chip scale package (WLCSP).
在圆片规模上开始加工，结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。
The WLP technology that initiates processing from Wafer-Level and finishes in chip scale will be applicable on a daily broadening scale in plane array FCP.
德州仪器TMP006 /B红外热电堆传感器的晶片级封装（图3）提供非接触式温度传感器用于保健，美容，和火焰检测应用。
The Texas Instruments TMP006/B Infrared Thermopile Sensor in a Chip-Scale Package (Figure 3) provides non-contact temperature sensing for use in health, beauty, and flame-detection applications.
它以毫秒级的精度封装时间上的某个瞬间时刻。
It encapsulates an instant in time with millisecond precision.
所有层的功能都封装为SOA服务，使得在广泛可访问、灵活和可重用的构件基础上组成企业级信息服务成为可能。
Functions at all layers are encapsulated as SOA services, making it possible to compose enterprise-level information services out of widely accessible, flexible and reusable building blocks.
AspectJ在AOP技术中差不多是惟一支持这一级别的封装的。
AspectJ is nearly unique among AOP technologies in supporting encapsulation at this level.
在完成整体结构圆片级真空封装的同时，通过引线腔结构方便地实现了中间电极的引线。
Through the silicon bonding, we achieve a wafer-level vacuum package, and the wire-bonding PAD is made after the fabrication is complete.
圆片级芯片尺寸封装（WL-CSP）工艺是在固态芯片尺寸玻璃外壳中装入芯片。
This wafer level chip size package (WL-CSP) process encases the die in a solid die-size glass shell.
在完成整体结构圆片级真空封装的同时通过引线腔结构方便地实现了中间电极的引线。
Through the silicon bonding, the wafer-level vacuum package is achieved and the wire-bonding PAD is made after all the fabrication work is finished.
论述了封装结构、工艺流程及封装可靠性，并阐述了板级组装工艺过程和互连可靠性。
The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.
系统级的凝聚特征将设计知识、几何形状以及联接关系等封装起来，克服了传统特征在功能语义表达上的不完备性。
Encapsulating design knowledge, geometry form and conjunction relationship, the agglomerated feature in system-level is generated to maintain the whole semantic elements of a function.
1D-板级扇出低成本的多晶片小外形封装；
1D- panel level fanout low cost multi-die small form factor packaging;
随着器件功能的日益复杂和封装的多样化，实现器件级的鉴定越来越困难。
Due to the complicity of the component's functions and the variety of device's packaging, the component level testing is getting more and more difficult.
该软件可用于封装，电路板及系统级CFD模拟，包括自然对流、强制对流和辐射传热。
This software can be used for package -, board - or system-level CFD simulation, including natural and forced convection and radiation heat transfer.
该器件的WLCSP(晶圆级芯片尺寸封装)是超小型，简化电路板设计。
The device's WLCSP (Wafer Level Chip Scale Package) is ultra compact, simplifying board design.
该器件的WLCSP(晶圆级芯片尺寸封装)是超小型，简化电路板设计。
The device's WLCSP (Wafer Level Chip Scale Package) is ultra compact, simplifying board design.
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