第一栅极与第二栅极分离。
第一栅极及第二栅极分开配置于所述基底上。
The first gate and the second gate are separately disposed on the substrate.
第一栅极的第一宽度与第二栅极的第二宽度不同。
Notably, the first length of the first gate is different from the second length of the second gate.
此外，第一栅极与第二栅极的共用掺杂区域配置于基底中。
Furthermore, the common doped region of the first gate and the second gate is disposed in the substrate.
晶体管栅极可以由具有不同功函数的第一栅极导体和第二栅极导体形成。
The transistor gate may be formed from first and second gate conductors with different work functions.
在给定晶体管中的第一栅极导体和第二栅极导体的相对尺寸控制晶体管的阈值电压。
The relative sizes of the first and second gate conductors in a given transistor control the threshold voltage for the transistor.
本文描述了用于装配电子枪时控制阴极与第一栅极间距的光纤传感器的结构及其测量系统。
The construction and measurement system of fiber-optic sensor for monitoring the distance between cathode and first grid during assembly of electron gun are described.
它采用四极枪结构，两个栅极，第一栅极采用双层同心球面网，第二栅极外还添加了屏蔽筒。
The first grate has double spherical nets with the same center and outside the second one there is a shield cylinder to make electron congregate.
该耗尽模式部分由该第二栅极栅控，并且适于工作于耗尽模式且可屏蔽该第一栅极免受电压负荷影响。
The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.
该第一栅极及第二栅极电性相连，且该第二栅极连接一接触线，以连接至一焊垫以传输栅极控制信号。
The first gate and the second gate are electrically connected, and the second gate is connected with a contact wire to be connected to a pad for transmitting a gate control signal.
所述电阻式存储器单元包括第一栅极、第二栅极、共用掺杂区域、接触窗插塞、位线以及电阻式存储器元件。
The resistive memory cell comprises a first gate, a second gate, a common doped region, a contact plug, a bit line and a resistive memory element.
以及一电压提升装置，用以控制该第一MOS晶体管及该第二MOS晶体管的栅极；
The voltage lifting device controls grid electrodes of the first MOS transistor and the second MOS transistor.
一种薄膜晶体管阵列基板，其 包括：第一导电图案组，包括薄膜晶体管的栅极和与该栅极相连的选通线；
Said thin-film transistor array substrate comprises a first conductive pattern group having grids of the thin-film transistor and select lines connected with the grids;
一种薄膜晶体管阵列基板，其 包括：第一导电图案组，包括薄膜晶体管的栅极和与该栅极相连的选通线；
Said thin-film transistor array substrate comprises a first conductive pattern group having grids of the thin-film transistor and select lines connected with the grids;
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