课程目标，数字逻辑，硬件描述语言。
Course Objectives, Digital Logic, Hardware Description Languages.
VHDL是一种特殊的硬件描述语言。
试验程序由VHDL硬件描述语言编写。
The program is compiled with VHDL(hardware description language).
视觉硬件描述语言?。
第三章介绍了系统实现的硬件描述语言VHDL。
Chapter three introduces the VHDL - a sort of-hardware design describe language.
CDL语言是国际上广泛使用的计算机硬件描述语言。
CDL is a wide-spreading computer hardware description language.
EDA的一个重要特征是使用硬件描述语言来完成设计。
EDA is an important feature of the use of hardware description language to complete the design.
PMIC的设计目的是获取模拟图表和数字硬件描述语言。
The PMIC design intent is captured as analog schematics and digital HDL.
每一种硬件描述语言都采用了离散事件语法对系统进行建模。
Every kind of hardware description language adopted discrete event of system modeling of grammar.
提出了用硬件描述语言VHDL描述RAID通道适配器模型。
The model of RAID channel adapter de-scribed by VHDL is put forward.
VHDL硬件描述语言基础，非常好的一本书，有时间不妨看看！
VHDL hardware description language based, a very good book, time to take a look!
这是一个用硬件描述语言来设计的交通灯程序，和实用，很经济。
This is a hardware description language used to design the traffic light procedures, and practical, it is economic.
该软件完成对硬件描述语言实现的密码算法IP核进行功耗分析。
The simulation software conducts the power analysis of cryptographic algorithm IP core which is described by hardware language.
越来越多的工程师开始使用硬件描述语言和高级综合工具进行设计。
More and More engineers gradually begin to design by using hardware description languages (HDLs) and sophisticated synthesis tools.
VHDL作为数字系统的硬件描述语言已应用多年，并取得了成功。
VHDL has been successfully used for years as a hardware description language to digital system.
采用VHDL硬件描述语言设计一种再生视频复合消隐信号的专用芯片。
In this paper, a kind of chip of video complex black signal is described with VHDL.
本文介绍了一种通用硬件描述语言——UHDL及其编译器的设计与实现。
UHDL-A Universal Hardware Description Language and its compiler is presented in this paper.
本文采用VHDL硬件描述语言对FPGA编程实现了高精度脉冲发生器。
In this thesis, VHDL hardware description language was applied to program FPGA to realize high accurate pulse generator.
该抢答器单元电路的软件设计分别利用原理图设计、硬件描述语言设计完成。
The circuit software was designed using schematic diagram and hardware description language (VHDL) respectively.
采用模块化设计方法对CPLD进行设计，并给出了硬件描述语言的具体结构。
With blocking means in CPLD design, the structure of HDL (hardware describe language) program is also given.
VHDL作为一种IEEE标准的电路硬件描述语言，正广泛地被电子技术人员使用。
VHDL are widely used by electronic technology professional as IEEE standard circuit hardware description language.
VHDL作为一种电路硬件描述语言，目前正在被越来越多的电子技术设计人员所应用。
As a hardware description language, VHDL has being used more and more by electronic circuit designers.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
CDL语言是国际上广泛使用的计算机硬件描述语言，CDL/MP是CDL语言的扩充。
CDL is a wide-spreading computer hardware description language. CDL/MP is an ex pausion of the CDL.
每个模块的设计方法是首先建立数学模型，然后用混合信号硬件描述语言完成数学模型的功能。
The design method of each module is modeling mathematic models firstly, and then using the mixed signal hardware description language to realize the module.
数字逻辑系统的设计离不开计算机辅助设计CAD工具的帮助，尤其是VHDL硬件描述语言。
Now, many digital logic systems cannot do without computer aided design CAD, especially the VHDL Hardware Description Language.
最后是软件部分的编程，包括CPLD部分的硬件描述语言程序设计，和DSP部分相关的程序设计。
At last we describe the software design, including software design of CPLD basing on VHDL and software design of DSP.
硬件描述语言(VHDL)是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
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