采用VHDL硬件描述语言设计一种再生视频复合消隐信号的专用芯片。
In this paper, a kind of chip of video complex black signal is described with VHDL.
该抢答器单元电路的软件设计分别利用原理图设计、硬件描述语言设计完成。
The circuit software was designed using schematic diagram and hardware description language (VHDL) respectively.
阐述了用硬件描述语言设计仲裁逻辑的具体过程，给出了逻辑状态机和转换关系。
The design procedure of arbiter logic by hardware description language and state with transform conditions are also demonstrated.
该设备以FPGA为核心，使用VHDL硬件描述语言设计并实现了异步串行通讯、测试设备的自检、引信产品的检测等几大功能。
Based on FPGA the equipment with the functions of asynchronous serial data transfer, self-test capability, fuze product test and so on is designed and realized by VHDL program.
本文利用VHDL硬件描述语言设计了一种SVPWM信号发生器，该信号发生器不仅成功实现了输入时间信号到SVPWM触发信号的转换，而且具有良好的抗干扰能力。
In this paper, a SVPWM signal generator is designed with VHDL. This signal generator can transform time signal into SVPWM trigger signal successfully with good anti-jamming capability.
EDA的一个重要特征是使用硬件描述语言来完成设计。
EDA is an important feature of the use of hardware description language to complete the design.
每个模块的设计方法是首先建立数学模型，然后用混合信号硬件描述语言完成数学模型的功能。
The design method of each module is modeling mathematic models firstly, and then using the mixed signal hardware description language to realize the module.
越来越多的工程师开始使用硬件描述语言和高级综合工具进行设计。
More and More engineers gradually begin to design by using hardware description languages (HDLs) and sophisticated synthesis tools.
这是一个用硬件描述语言来设计的交通灯程序，和实用，很经济。
This is a hardware description language used to design the traffic light procedures, and practical, it is economic.
介绍了利用VHDL硬件描述语言结合FPGA可编程器件进行数字钟的设计，并通过数码管驱动电路动态显示计时结果。
The paper introduces the design of digital clock based on FPGA and VHDL, the time of clock can be displayed with the digital driving circuit.
数字逻辑系统的设计离不开计算机辅助设计CAD工具的帮助，尤其是VHDL硬件描述语言。
Now, many digital logic systems cannot do without computer aided design CAD, especially the VHDL Hardware Description Language.
采用有限状态机设计方法，使用VHDL硬件描述语言编程，并在EDA工具软件平台上进行了仿真和下载。
A design method by usage of finite state machine and VHDL hardware description language to develop the program is adopted, then it is simulated and downloaded on the EDA software platform.
采用模块化设计方法对CPLD进行设计，并给出了硬件描述语言的具体结构。
With blocking means in CPLD design, the structure of HDL (hardware describe language) program is also given.
本文介绍了一种通用硬件描述语言——UHDL及其编译器的设计与实现。
UHDL-A Universal Hardware Description Language and its compiler is presented in this paper.
VHDL作为一种电路硬件描述语言，目前正在被越来越多的电子技术设计人员所应用。
As a hardware description language, VHDL has being used more and more by electronic circuit designers.
用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。
The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.
本文主要通过FPGA器件，利用HDL硬件描述语言，初步完成了USB设备控制器的设计和实现。
This thesis using FPGA devices and VHDL hardware description language to completed the design and realization of USB equipment controller.
VHDL作为一种通用的硬件描述语言，在电路设计中被广泛使用。
As a common kind of language for description of hardware, VHDL was once widely applied in circuit design.
PMIC的设计目的是获取模拟图表和数字硬件描述语言。
The PMIC design intent is captured as analog schematics and digital HDL.
本文引入了电子设计自动化(EDA)技术，在EDA平台上使用硬件描述语言(VHDL)完成对硬件功能描述，使硬件设计更加灵活。
The paper introduce the technique of EDA, on it, logical function has been stigmatized by VHDL language, the design of hardware become more flexible.
到20世纪80年代，已出现了上百种硬件描述语言，对设计自动化曾起到了极大的促进和推动作用。
Have already appeared up to 100 hardwares a description language to the 80's in 20 centuries, to design the automation once had to promote and push a function biggest.
利用CPLD复杂可编程逻辑器件，结合VHDL硬件描述语言，设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
硬件描述语言(VHDL)是数字系统高层设计的核心，是实现数字系统设计新方法的关键技术之一。
VHDL is considered as a core of digital system design and a key technique of implement digital systems design.
用硬件描述语言VHDL对可编程器件FPGA进行功能模块设计、仿真综合，可实现VGA控制器显示各种图形、图像、文字等。
The design of functional module and simulation and synthesis based on FPGA by using VHDL can be realized on VGA Controller, which can display the figure, image, character and the like.
最后是软件部分的编程，包括CPLD部分的硬件描述语言程序设计，和DSP部分相关的程序设计。
At last we describe the software design, including software design of CPLD basing on VHDL and software design of DSP.
CPU内核采用VHDL硬件描述语言输入，结合流行的EDA设计、综合、仿真工具，最后在FPGA上实现该内核。
The reference CPU core use VHDL language input, make logic synthesis and simulation through the popular EDA tools, then it was implemented in FPGA.
该设计采用可编程逻辑器件，VHDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and VHDL is used as input tools, which have simple software interface, good reliability and practical value.
该设计采用可编程逻辑器件，ABEL HDL硬件描述语言为输入工具，接口简单，可靠性高，具有一定的实用价值。
The programmable logic device and ABEL-HDL is used as input tools, which have simple software interface, good reliability and practical value.
VHDL语言作为先进的硬件描述语言，也以其灵活、简洁的设计风格再电路设计中发挥着越来越重要的作用。
The VHDL language as an advanced hardware description language is playing a more and more important role in digital circuitry designs with its nimble and simple design style.
VHDL语言作为先进的硬件描述语言，也以其灵活、简洁的设计风格再电路设计中发挥着越来越重要的作用。
The VHDL language as an advanced hardware description language is playing a more and more important role in digital circuitry designs with its nimble and simple design style.
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