算法级抗攻击方案以及2电路级抗攻击方案。
Based on the necessary condition of the above two kinds of attacking methods, we proposed several kinds of countermeasures from two levels: 1 algorithm level and 2 circuit level.
本文介绍了一种将MOS电路级描述转换成逻辑级描述的统一方法。
An unified method for converting MOS circuit level description into logic level description is presented.
电路级综合实验结果表明：本方法可以快速设计出满足性能指标的运算放大器。
It has been demonstrated that this approach can design an op-amp to meet the requirements rapidly.
论文从系统级、模块级、电路级和物理级对非挥发性存储器芯片设计中的关键设计技术进行了研究。
In this paper, we design this non-volatile memory chip in system level, module level, circuit level and physical level.
网络借鉴了电路级代理工作的基本原理，以应用协议的会话数据流为对象，对信息系统进行控制和管理。
The concept adopted basic theory of circuit-level proxy. Taking session data flow of application protocols as its objective, VAN controlled and managed integrated information systems.
在设计者进行系统和电路级设计时，时常会将要实现的逻辑功能或操作较为平均地分配到时序中的各个阶段，称之为逻辑平衡设计。
This paper focuses on the high performance very large scale integrated circuits design using the concept of logic balance at the first time.
这证明了天线，无线电芯片，控制电路，和微米级的光源可以被集成在隐形眼镜镜片上，并且在眼睛上正常工作。
This verifies that antennas, radio chips, control circuitry, and micrometre-scale light sources can be integrated into a contact lens and operated on live eyes.
石墨烯可能成为纳米级的“电子电路试验板”，希恩说。
Graphene could be a sort of nanoscale "electronic breadboard", says Sheehan.
而且一个研究团队组建了一台拥有定制的集成电路的超级计算机，定制的集成电路极大地提高了蛋白质折叠计算的速度，允许在毫秒级的时间精度上进行仿真。
And one research team built a supercomputer with customized integrated circuits that dramatically speed protein-folding calculations, allowing simulations on the time scale of milliseconds.
作为纳米级存储电路及相似设备的一项候选逻辑开关，这种银触须开关具备以下几个非常有吸引力的特征。
As a candidate logic switch for nanoscale memory circuits and similar devices, the silver whisker switch has several attractive features.
设备设计师能通过审慎地选择输入输出级电路的拓扑和共模阻抗来最小化失配或“非平衡”的效应。
Equipment designers can minimize the effects of these mismatches or "unbalances" through judicious choices of input and output stage circuit topologies and common-mode impedances.
论述了电爆炸导体的爆炸机制，设计了两个电爆炸断路开关的电感储能电路，通过斩波来产生一个纳秒级大电流的单触发脉冲。
Through studying the mechanism of the electric exploding, an inductive storage circuit with two electric explosive switches is designed to produce shot nanosecond pulse by chopped wave.
LOP电路设计采用VHDL语言门级描述，已通过逻辑仿真验证，并在浮点加法器的设计中得到应用。
The LOP circuit module is described in gate level with VHDL, which has passed the logic simulation and verification. It is applied to the design of floating-point adder.
本文介绍了该逻辑学和其在计算纳米级门电路的概率分布方面的应用。
This paper describes the logics and the using in computing the probability distribution of the nano-gate states.
与一些音量控制置于输入端的电路不同，这个前级放大器的特征噪声能够随同信号一起衰减。
Any noise characteristic of the preamp circuit is attenuated along with the signal, unlike circuits where the volume control is before the input.
同直流信号直接耦合处理相比，交流信号耦合虽然要增设调制解调装置，但对后级信号处理电路的器件要求更低，信噪比更高。
Compared with DC coupling signal processing, it need lower requirement of signal processing circuit and have the merit of high signal-to-noise performance although it require the device of modem.
结合共射极单级放大电路的分析过程，说明了EW B软件的使用方法及对实际电子线路进行仿真的基本步骤。
Combining the analyzing process of oneway amplifying circuit, it illustrates the usage of EWB software and the basic steps of emulating the actual electron magnitudes of way.
寄存器传输级（RTL）描述是目前应用最广泛的电路设计描述形式。
The Register Transfer Level (RTL) behavioral descriptions are widely used in IC designs.
讨论了数字电路的逻辑级模拟中元件传输延迟模型、元件状态值模型的建立，逻辑模拟的算法以及元件计算的方法。
Discuss the three aspets of the logical-level simulation theory of digital circuits: the construction of delay model and multi-state model, simulation algorithms, and methods of component computation.
此外，本文提出元件级电路设计的卡诺图方法和代数方法。
Besides, the Karnaugh map method and algebra method are presented for designing component level circuits.
介绍一种采用DAC0832作为数控衰减器构成的自动增益控制电路，其外围电路非常简单，受控等级可达256级。
Presented in this paper is a digital AGC circuit that is constituted with digital attenuator DAC0832. Its controlled grade can reach 256 and the external circuit is very simple.
采用两路结构相同的最大电流选择电路实现输入级总跨导的恒定。
The constant gm of input stage is achieved by two identical maximum current selection circuits.
核心电路为两级直接耦合差分放大器。
The core circuit is two stages of direct-coupled difference amplifier.
集成电路设计在寄存器传输级的设计方法已经非常成熟。
核电站1e级电路线槽系统。设计，安装和鉴定的标准。
Raceway Systems for Class 1e Circuits for Nuclear Power Generating Stations, Criteria for the Design, Installation, and Qualification of.
系统中采用线性光偶和隔离电源，使前级放大电路和后级电路隔离，保证了系统的安全性。
The EMG preamplifier circuit and other circuits are isolated by high-linearity octocoupier and isolated power that reject the industry interference and improve the security of the system.
随着集成电路工艺与技术的飞速发展，集成电路已经进入系统级芯片阶段。
With the rapid development of semiconductor technology, integrated circuit has stepped into a new era of SOC.
在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
在电路设计过程中，对后级接口电路进行了最优化设计，采用VHDL描述的方式实现了低压数字延时电路模块的设计。
In this paper, the optimization method was used to design the interface circuit, and use VHDL description to design low voltage digital delay timer.
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