本文提出了一种简单有效的、运用于模拟和混合信号电路的测试方法。
This paper presents a simple and efficient testing scheme for analog and mixed-signal circuits.
仿真结果和测试结果表明，利用图解和CAD相结合的方法能够方便、有效地进行电路设计，提高设计效率。
The simulation and test results show that the hybrid method of Graphic and CAD is able to design circuit efficiently and easily, save development time and enhance design efficiency.
此外，在很多情况下，一些电路只有一个可测试点，也就是它的输出端，传统的方法根本无法对它们进行有效诊断。
In addition, in many cases, there is only one testing point for some circuits, that is, its output, traditional methods are unable to effectively carry out their diagnosis.
实验证明，该方法简单有效，是一种可行的模拟及混合电路测试方法。
The experimental results show that it is simple and efficient, thus allowing a feasible-scheme for analog and mixed-signal circuits.
全扫描设计通过提升电路的可控制性和可观察性，大大降低了测试生成的复杂度，被认为是最有效的可测性设计方法之一。
Full-scan design which upgrades the circuit in the controllability and observability greatly reduces the complexity of test generation, which is considered the most effective method of DFT.
利用该方法，既可以快速得到DAC的静态参数，又提高了测试精度，使得测试电路简单、紧凑和有效。
Using the BIST structure, we can calculate the static parameters of DAC's quickly, and improve the accuracy of testing which makes the circuit simple, compact and efficient.
工业测试实例实验表明，该算法能够有效地优化电路时延，满足时延约束。
Experimental results show that the algorithm can optimize the timing of circuit efficiently and the timing constraint is satisfied.
通过添加测试引脚、设计专用测试模式，内建自测试等方法有效的解决了该芯片电路的功能测试和电气性能测试。
The top metal test pad, special test mode and BIST are adopted in the IC circuits to solve the IC test problem about the chip function test and electric character test.
试验数据显示，该模型和测试生成算法不仅对生成测试序列是有效的，而且对于电路描述的可测性分析也有一定的帮助。
The results show that the circuit model and the test generation algorithm are not only effective for generating test sequence but also can help for the testability analyse.
经过算法验证和样片测试，有效值电路设计完全满足设计规格。
It is confirmed that the result of the design meets the specification by the algorithmic verification and test of sample.
文中提出了显式冗余的队列循环优化算法，完全消除了此类冗余，从而有效地减少了生成电路的基片面积，提高了电路的可测试性。
This paper proposes a queue loop optimization algorithm to remove explicit redundancy completely which decreases the circuit area and improves the testability.
为了验证该方法的有效性，本文针对一块以MC 6800为微处理器的电路板进行了测试程序开发。
To verify the approach, we generate the test program for a circuit board based on MC6800 microprocessor.
介绍用高性能CS5460A设计数字真有效值电参数测试仪的原理、方法，给出了部分电路。
The principle and method of design of a digital TRMS electrical parameter test instrumentation by use of high performance CS5460A were introduced, its circuit was also partially given.
在ITC'02基准电路上的实验结果验证了基于对平衡测试调度算法的有效性。
Experimental results for two ITC '02 SOC benchmark show that the pair balance-based test scheduling achieves less test time compared to the previous approaches.
通过并行测试结构，同时对几条受害线进行测试，有效减小了测试时间和电路面积。
With parallel test infrastructure, victim lines could be tested simultaneously, so that the test time and circuit area can be reduced efficiently.
直流参数测试是集成电路测试技术的重要组成部分，能够快速有效的检测芯片的性能，受到集成电路测试行业的高度重视。
DC parametric testing is an important component of IC test, it has got more attention from IC test industry, because it could detect the performance of the IC quickly and efficiently.
直流参数测试是集成电路测试技术的重要组成部分，能够快速有效的检测芯片的性能，受到集成电路测试行业的高度重视。
DC parametric testing is an important component of IC test, it has got more attention from IC test industry, because it could detect the performance of the IC quickly and efficiently.
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