用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。

The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.

youdao

用VHDL（甚高速集成电路硬件描述语言）有限状态机设计了数据采集时序的控制电路。

The sequence control circuit of DATA collection is designed with finite state machine(FSM) of VHDL.

youdao