标准逻辑单元，存储电路设计及输入输出单元设计。
标准逻辑单元，存储电路设计及输入输出单元版图设计。
此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
本文提出在ASIC综合技术中基于标准单元库的多级逻辑函数分解技术。
The decomposition of multilevel logic functions based on standard cell libraries used in ASIC synthesis is presented in the paper.
过滤器逻辑结构的模块化特别适宜用标准单元法来实现ASIC(专用集成电路)的版图设计。
The modularization of filter logical architecture is especially suitable for layout design of ASIC with standard cell.
文章分析了1149.4和1149.1标准的测试访问端口，以及测试逻辑结构和测试协议的异同，提出了模拟边界 扫描单元ABM和数字边界 扫描单元DBM的行为模型；
The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed, and behavior models for ABM and DBM are put forward.
文章分析了1149.4和1149.1标准的测试访问端口，以及测试逻辑结构和测试协议的异同，提出了模拟边界 扫描单元ABM和数字边界 扫描单元DBM的行为模型；
The test access port and test logic architecture and protocol of 1149.4 and 1149.1 standards are analyzed, and behavior models for ABM and DBM are put forward.
应用推荐