测试产品的仪器能够几乎立刻发现印刷电路板的缺陷，如果同样的任务由人来完成，那将花费很长的时间，而且不如机器准确。
A machine can examine a circuit board for faults almost instantly. A human would take far longer to do the same thing, and would be less accurate.
短路、开路测试完成以后，在线测试仪需要在同一时间对印刷电路板上的每一个器件进行测试。
After performing the shorts and opens test the in-circuit tester tests each component on a PCB assembly one at a time.
通过可测性设计，使该电路的测试难度及测试时间减少了将近一半。
By design for testability, both the degree of difficulty in testing and test time are reduced nearly one half.
对ISCAS’89和ISCAS’93基本测试电路的实验结果表明，此方法具有较好的计算精度和较短的计算时间。
The experimental results for some ISCAS' 89 and ISCAS' 93 circuits show that this method has the advantage of good accuracy and relatively small amount of calculation time.
在每次测试第一次通电过程中，控制动作时间比较电路启动，同时数字信号处理芯片自动记录每一路的热敏电阻的动作时间数据，并进行处理。
In the first course of testing, the operating time of compare circuit is brought into play, synchronously, digital signal processor clock all the testing circuits operating time and keep these .
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed with this method.
对于确定的测试向量集，用该方法构造的扫描链能使电路总的测试时间最少。
For a fixed set of test vectors, the overall test time can be minimized using the scan chain constructed by this method.
时序电路专用测试系统的研制实现了HPG模块和引信本体中时序电路测试的自动化，缩短了测试的时间，提高了测试的准确性。
The design of timing circuit test system realized the test automation of timing circuit in fuse and HPG chip, reduced the test time, raised the test accurence.
该扫描路径上的延迟减少对外部缓冲器的需求，进而在集成电路扫描测试时避免保持时间违反。
The delay in the scan path reduces the need for external buffers to avoid hold-time violations during scan testing of integrated circuits.
可测性设计的本质就是使电路容易测试，它根本上也要求测试时间的减少。
The essence of DFT is to make the electric circuits test easily, it also requests to decrease the test time basically.
本算法充分利用了系统的可测性电路及资源，测试复杂性较低，执行时间短，故障定位精度也较高。
The testability resource of hardware is fully considered, so that the test complexity and testing time are largely reduced and fault location is well sa…
通过并行测试结构，同时对几条受害线进行测试，有效减小了测试时间和电路面积。
With parallel test infrastructure, victim lines could be tested simultaneously, so that the test time and circuit area can be reduced efficiently.
该算法用于对一组标竿电路进行测试，和传统模拟退火算法得出的结果相比，在布局效果上和时间性能上均显示出优越性。
This algorithm was applied to test a set of benchmark circuits, and experiments show its advantages in placement results and time performance by comparing wit...
集成电路制造商在测试上的成本也越来越高，尤其是在建立大规模的测试版图时的时间成本与人力成本。
IC manufacturers' const testing increases to more high, especially in the establishment of a large-scale chip of the test structure of time and labor costs.
集成电路制造商在测试上的成本也越来越高，尤其是在建立大规模的测试版图时的时间成本与人力成本。
IC manufacturers' const testing increases to more high, especially in the establishment of a large-scale chip of the test structure of time and labor costs.
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