实时时钟模块提供的是分为模拟和数字域名。
The real time clock module provides is divided into an analog and a digital domain.
并对存储器的电平转换以及时钟模块的配置进行了详细的分析。
Otherwise, the electric level transform of memorizer and the configuration of clock module are analyzed in detail.
在FLL时钟模块旨在满足要求的低系统成本和低功率消耗。
The FLL clock module is designed to meet the requirements of both low system cost and low power consumption.
实时时钟模块是典型的字符设备也是工业控制系统中的重要组成部分。
The RTC module is a typical char device as well as an important part of Industrial Control System.
实时时钟模块是典型的字符设备也是工业控制系统中的重要组成部分。
The power manager unit and the nodes sleep period are controlled by an RTC(real time clock) chip.
系统硬件部分包括GPS接收机、GPS时钟模块、脉冲峰值采集卡及工控机。
The hardware includes GPS receiver, pulse peak acquisition card, GPS clock module and industrial computer.
实时时钟模块的维护工作和时间“非易失性”，或当一个永久的记忆集成电路关机参数。
A real time clock module maintains operating and timing parameters in "non-volatile" or persistent memory when an integrated circuit is powered down.
系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。
The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.
水下武器系统综合检测系统采用模块化设计思想，由信号发生器模块、A/D模块、D/A模块、实时时钟模块、液晶及打印机模块等组成。
The synthesized test system for underwater weapon system adopts a modularized structure with signal generator, A/D converter, D/A converter, real-time clock, printer and LCD screen.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
STC 89c52单片机模块：由单片机STC 89c52单片机、复位电路、时钟电路等构成，是整个系统的核心。
STC89C52 microcontroller modules: microcontroller STC89C52 single-chip, reset circuit, clock circuit constitute the core of the whole system.
首先讨论了逻辑时钟方法及逻辑时钟的修改算法，然后介绍了自行研制的分布式s4系统中逻辑时钟监控器模块的实现方法。
Firstly it discusses the approach of logical clock and revise algorithm of logical clock, then introduces the implementation approach of logical time monitor module in distributed S4 system.
在幸存路径管理模块采用门控时钟的方法，有效地降低了对幸存路径存储部分的功耗。
SMU module adopts the clock-gating method was applied to the survivor path storage block, reduce the survivor path storage memory power dissipation effectively.
设计了一种新型平滑度仪，详细描述了控制器、数据采集、人机接口和实时时钟等模块的具体选型及设计；
A new smoothness tester has been designed and accomplished. This paper presents in details the module design of controller, data acquisition, man-machine interface and real clock.
采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。
The FIFO module in FPGA was applied to realize the pixel clock modification and the data saving and taking.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
在数字系统中各个模块所需的时钟频率往往不相同，通常采用分频的方法由系统时钟得到所需频率。
Different components in a digital system often need different working frequencies, the way we often used is clock division from the system clock.
本系统主要包括GPS同步时钟和通信协议转换模块，二者之间通过RS- 485总线进行连接。
The GPS synchronous clock and the conversion devices are linked up with RS-485 bus.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
被禁用的模块中包含的相关逻辑和时钟树会因此停止消耗能量。
Associated logic and clock trees contained in a disabled module will therefore stop consuming power.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
硬件电路设计主要包括中央处理单元电路、时钟电路、软件用汇编语言来实现，主要包括主程序、时光设置子程序等软件模块。
Hardware circuit design includes a central processing unit circuit, clock circuit, assembly language software to achieve, including the main program, subroutine, such as set-up time software modules.
时基模块为控制模块和传输模块提供时钟；
The time base module provides clocks for the controlling module and the transmitting module.
设计了一种高精度时间间隔测量模块，该模块由单片机控制，采用脉冲计数原理，通过测量时间间隔内高频参考时钟个数，得到被测时间间隔的精确值。
Based on pulse counting principle, the high precision time interval can be obtained by measuring the number of the high-frequency reference clock through it.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
本论文的嵌入式硬件环境，包括CPU的外围时钟电路，复位电路，存储器单元，LCD模块，触摸屏，键盘，FLASH，SDRAM，网络接口等部分。
The embedded system in this thesis include CPU , memory part , LCD part, touching screen, keyboard, FLASH, SDRAM and internet interface and so on.
本时钟同步管理方案由GPS通信模块、操作维护、软件控制管理三部分组成，重点研究了软件锁相控制算法，并给出了测试数据。
The solution on clock synchronization composes with GPS, operation maintenance, software locking phase control. And the last one is researched specially, and some test data are given.
通过增加少许电路结构，解决了由于内部多时钟以及多个嵌入式存储器模块的结构带来的影响可测性要求的问题。
With a very small extra number of circuits, the testability problem was removed which is caused by the asynchronous clocks and embedded memories.
锁相环在微处理器领域中的一个重要应用就是为系统提供片内时钟，它是微处理器时钟电路中的核心模块。
One important application of PLL in microprocessor is to provide on-chip clock for the system. It has been a core module of microprocessor.
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