系统时钟恢复是数字电视系统设计中的难点。
分析了应用于时钟恢复电路中的相位插值器。
In this paper, a detailed analysis of a phase interpolator for clock recovery is presented.
快速载波和位时钟恢复是突发模式传送系统的一个关键因素。
Rapid carrier and clock recovery is a key technique in burst mode transmission.
介绍了一类基于双向输入型鉴相器锁相环技术的时钟恢复系统。
The paper introduces a kind of clock recovery system based on phase-locked loop with bi-directly incident phase-comparator.
介绍了一个应用在移动支付系统里的全集成载波时钟恢复电路。
This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application.
码型转换是实现非归零(NRZ)信号全光时钟恢复的关键技术。
Pattern conversion is the key technology for all-optical clock recovery from non-return-to-zero (NRZ) signal.
本文主要研究应用于光分组交换网络的全光时钟恢复(提取)技术。
This dissertation focuses on the optical clock recovery techniques in optical packet switching (OPS) network.
时钟同步的同步剩余时标法、自适应时钟恢复法和线路时钟恢复法，应根据组网情况合理选择。
According to the instance of organizing network, the ways of generating synchronization clock was selected such as spare timing…
模拟电路的性能难以满足需要，例如，在支路时钟恢复电路中，模拟锁相环难以满足噪声抑制要求；
The performance of the analog circuit is difficult to satisfy the need, such as the analog pll can't satisfy the requirement of noise restrain in digital clock extracting circuit.
更高速率系统的研制目前也在开展中。时钟恢复电路(CRC)是光纤通信和许多类似数字通信领域中不可缺少的关键电路。
Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission.
系统时钟恢复是数字电视系统设计中的难点。从研究数字电视接收系统出发，根据实际需要深入探讨并提出了一种基于缓存技术的系统时钟处理方案。
System clock recover is the key in digital TV system. The paper proposes a scheme of clock settlement based on buffer technology from researching DTV receiving system.
本论文给出了时钟恢复电路的基本原理以及采用PLL型时钟恢复电路的完整的电路设计、模拟结果和版图设计，以及将时钟恢复电路集成到光接收机后的测试结果。
The thesis presents basic principle of CRC and rounded circuit design, simulation results, layout design and testing results of a PLL type CRC, which is incorporated in a optic-fiber receiver chip.
人体生长激素也被发现是一种起恢复作用的酏，虽然实验表明它也不能将生命时钟倒转。
Human growth hormone has also been touted as a restorative elixir, even though research has indicated that it can't turn back the clock.
可以预计，只要在器件上作某些更换，亦可制成工作速率更高的时钟数据恢复模块。
It is estimated that a data and clock recovery module with a higher operating rate is available only if some devices are changed.
设计了一个数字时钟数据恢复电路，采用相位选择锁相环进行相位调整，在不影响系统噪声性能的前提下大大降低了芯片面积。
A phase selection PLL is adopted to adjust the phase of the recovered clock, and the chip area of the recovery circuit is greatly reduced without sacrificing the noise performance of the system.
P PM无线光通信的关键问题之一在于时隙时钟与帧同步信号的恢复。
One of the most critical points in optical PPM radio communication lies on the recovery of slot clock and frame synchronization signal.
与传统并行数据恢复电路相比，该电路不需要本地参考时钟，并且恢复出的并行数据是位同步的。
Compared with conventional circuits, the recovered parallel data is bit-synchronous, and the reference clock is avoided.
在突发式的接收模块中，逻辑电平的恢复和时钟数据的恢复是其关键的问题。
The most difficult problem in burst mode receiver would be signal logic level recovery and data and clock recovery.
基于SERDES的串行通信过程中采用时钟和数据恢复技术（CDR）代替同时传输数据和时钟，从而解决了限制数据传输速率的信号时钟偏移问题。
Serial communications based on SERDES adopt the clock_data recovery(CDR) instead of both data and clock transmitting, which solve the problem of clock skew.
在发送端时钟频率随时间变化的情况下，以较低的成本和较简单的电路实现，保证了接收端采样数据及音频数据恢复的准确性。
Because clocking frequency of sending terminal is changed with times at lower cost and simple circuit, accuracy of receiving end sampled data and audio - data recovery is assured.
本系统利用集成时钟和数据恢复芯片SY87700L实现了可靠的位同步。
This system select integrate chip SY87700L to realize bit synchronizing reliably .
从时钟利用主时钟发来的时钟信号，通过数字锁相环恢复出本地时钟信号。
With the signal from the master clock, the slave clock is able to recover an accurate local clock signal using a Clock Recovery Phase Locked Loop (PLL).
重启时钟会将其当前迭代恢复为1。
重启时钟会将其当前迭代恢复为1。
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