系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
该电度表的控制电路主要由信号检测、实时时钟、输出控制电路及68hc 705c8单片机组成。
The control circuit of the Kilowatt-hour meter consists mainly of the circuit of signal detection, real-time clock and control of output, and it also consists of 68hc705c8 single chip computer.
可以提供输入及输出用于引入及输出精确参考时钟信号。
Inputs and outputs are provided for bringing in and outputting precision reference clock signals.
输出读数据信号的数据时钟出的内存存储单元。
An output read-data signal clocks the data out of the memory storage cells.
实验和模拟结果均表明：采用简化方案时转换输出的伪归零信号所包含的时钟分量的强度小于采用抽运探测方案的情况。
Both of them shows that the clock component contained in the converted PRZ signal obtained using the simplified scheme is weaker than that using the pump-probe scheme.
在串行数据输入（DI）或输出（DO）时使用的时钟信号。
Used as the synchronization clock when inputting (DI) or outputting (DO)serial data.
本控制系统以高性能8位单片机at89c52为核心，结合数据采集电路、信号输出电路、实时时钟电路、系统监控电路组成。
The control system is composed of AT89C52, a high-powered 8-bit microcontroller, data gathering circuit, real time circuit, data output circuit and system watch circuit.
频率比较器比较基准时钟和输出时钟的频率，并输出频率比较信号。
A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal.
相位比较器比较基准时钟和输出时钟的相位，并输出相位比较信号。
A phase comparator compares the phase of the reference clock with that of the output clock and outputs a phase comparison signal.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
输出时钟信号还具有可编程的相移和占空比调节等高级时钟变化功能。
The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.
它提供一个数据时钟输出(DCO)用于在输出端捕获数据，以及一个帧时钟输出(FCO)用于发送新输出字节信号。
A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
输出的时钟信号普适于多通道多相 位时钟应用，尤其适用于并行交替型模数转换器。
An output clock signal is universally suitable for the application of the multi-channel multi-phase clock, and is particularly suitable for a parallel alternate type analog-to-digital converter.
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