此功能对建立患者的综合视图至关重要，例如用于创建从不同设施上的治疗结果汇编而成的时序健康记录。
This functionality is critical in establishing a comprehensive view of a patient - to create a longitudinal health record compiled from their treatments at different facilities, for example.
对多维动态数据系统给出了全局主成分分析(GPCA)模型，并对时序立体数据表进行立体式的综合与简化。
Global principal components analysis (GPCA) model is presented to the multidimensional dynamic data system and the time sequence solid data table is three-dimensionally synthesized and simplified.
本文提出迁移函数法。用此方法可以解决多变量时序电路综合问题。
This paper presents a transition function method which can be extended to solve the synthesis problems of multiple variable sequential circuits.
时序逻辑综合是RTL综合系统设计中的一个重要部分。
Sequential logic synthesis is an important part of RTL synthesis system design.
本文提出三值触发器串接时序电路，用实例阐述综合方法。
The sequential circuit with ternary. flip-flops in series is proposed. The synthesis for the above circuit is discussed with an example.
研制了一种适用于脉冲中子测井仪的井下全谱采集控制综合时序发生器和阳极高压变换器。
One kind of down-hole full-spectrum acquisition controlling sequence generator and anode high-voltage converter is synthesized, which is suitable for pulsed-neutron synthesized logging tool.
由于该时序逻辑综合新方法在处理过程中要涉及解大型覆盖表的问题，为此提出满足压缩状态表约束关系的状态分配的简化算法。
This method, based on combinational logic minimization, proposes a new idea to proceed state assignment according to constrained. relation of compressed state table.
本文利用模糊集分析的方法，量化了影响导弹价值的因素，建立了关于导弹定价的时序模糊综合评判模型。
This paper USES the method of analysing fuzzy set and set up a model of time series multiple levels fuzzy synthetic judgement. And the factors affecting the missile price are explained at quantity.
负责带领整个团队实施芯片的综合、静态时序分析、逻辑一致性分析、后仿真、DFT、ATE、功耗控制。从芯片实现的角度对模块的RTL代码和芯片的RTL代码进行把关。
Lead ASIC frond-end design team to complete Synthesis, STA, Equivelant Check, Post Layout Simulation, DFT, ATE, Power Control. Make sure RTL code is ok for chip implement.
方法：采用有时序多指标决策的灰色关联分析法，对妇幼卫生保健项目实施效果进行卫生综合评价。
Method: the relative degree analysis for multiple attribute decision making with time series was used to assess the project comprehensively.
针对通用无线分组业务(GPRS)小区流量预测问题，对几种典型时序预测模型的性能进行了综合分析。
The performances of some classic time series prediction models were analyzed together concerning the traffic prediction of General Packets Radio Service (GPRS) cells.
提出了一种新的时钟偏斜规划算法，该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic syn thesis.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
最后利用FPGA平台实现了BIST的功能和时序验证，并通过综合、静态时序分析、自动布局布线实现了BIST系统的版图设计。
Finally USES FPGA platform for BIST functions and timing verification, and through design compiler, static timing analysis, automatic placing and routing to achieve a BIST system layout.
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