有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
有效地建立和表示时序逻辑电路的状态转移关系是应用模型检查方法验证时序逻辑电路的关键技术之一。
Building the transition relation of sequential logic circuit is one of the key technologies for applying model checking method to verify the sequential logic circuit.
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